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[AArch64] Sort switch cases (NFC) 

llvm-svn: 345786
This commit is contained in:
Evandro Menezes 2018-10-31 21:56:49 +00:00
parent 6c3f1692c8
commit 3a06c46470
1 changed files with 23 additions and 20 deletions
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43
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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@ -67,16 +67,30 @@ void AArch64Subtarget::initializeProperties() {
// this in the future so we can specify it together with the subtarget // this in the future so we can specify it together with the subtarget
// features. // features.
switch (ARMProcFamily) { switch (ARMProcFamily) {
case Others:
break;
case CortexA35:
break;
case CortexA53:
PrefFunctionAlignment = 3;
break;
case CortexA55:
break;
case CortexA57:
MaxInterleaveFactor = 4;
PrefFunctionAlignment = 4;
break;
case CortexA72:
case CortexA73:
case CortexA75:
PrefFunctionAlignment = 4;
break;
case Cyclone: case Cyclone:
CacheLineSize = 64; CacheLineSize = 64;
PrefetchDistance = 280; PrefetchDistance = 280;
MinPrefetchStride = 2048; MinPrefetchStride = 2048;
MaxPrefetchIterationsAhead = 3; MaxPrefetchIterationsAhead = 3;
break; break;
case CortexA57:
MaxInterleaveFactor = 4;
PrefFunctionAlignment = 4;
break;
case ExynosM1: case ExynosM1:
MaxInterleaveFactor = 4; MaxInterleaveFactor = 4;
MaxJumpTableSize = 8; MaxJumpTableSize = 8;
@ -98,11 +112,6 @@ void AArch64Subtarget::initializeProperties() {
MinPrefetchStride = 2048; MinPrefetchStride = 2048;
MaxPrefetchIterationsAhead = 8; MaxPrefetchIterationsAhead = 8;
break; break;
case Saphira:
MaxInterleaveFactor = 4;
// FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128;
break;
case Kryo: case Kryo:
MaxInterleaveFactor = 4; MaxInterleaveFactor = 4;
VectorInsertExtractBaseCost = 2; VectorInsertExtractBaseCost = 2;
@ -113,6 +122,11 @@ void AArch64Subtarget::initializeProperties() {
// FIXME: remove this to enable 64-bit SLP if performance looks good. // FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128; MinVectorRegisterBitWidth = 128;
break; break;
case Saphira:
MaxInterleaveFactor = 4;
// FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128;
break;
case ThunderX2T99: case ThunderX2T99:
CacheLineSize = 64; CacheLineSize = 64;
PrefFunctionAlignment = 3; PrefFunctionAlignment = 3;
@ -134,17 +148,6 @@ void AArch64Subtarget::initializeProperties() {
// FIXME: remove this to enable 64-bit SLP if performance looks good. // FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128; MinVectorRegisterBitWidth = 128;
break; break;
case CortexA35: break;
case CortexA53:
PrefFunctionAlignment = 3;
break;
case CortexA55: break;
case CortexA72:
case CortexA73:
case CortexA75:
PrefFunctionAlignment = 4;
break;
case Others: break;
} }
} }