forked from OSchip/llvm-project
parent
6c3f1692c8
commit
3a06c46470
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@ -67,16 +67,30 @@ void AArch64Subtarget::initializeProperties() {
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// this in the future so we can specify it together with the subtarget
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// features.
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switch (ARMProcFamily) {
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case Others:
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break;
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case CortexA35:
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break;
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case CortexA53:
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PrefFunctionAlignment = 3;
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break;
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case CortexA55:
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break;
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case CortexA57:
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MaxInterleaveFactor = 4;
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PrefFunctionAlignment = 4;
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break;
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case CortexA72:
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case CortexA73:
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case CortexA75:
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PrefFunctionAlignment = 4;
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break;
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case Cyclone:
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CacheLineSize = 64;
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PrefetchDistance = 280;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 3;
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break;
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case CortexA57:
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MaxInterleaveFactor = 4;
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PrefFunctionAlignment = 4;
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break;
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case ExynosM1:
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MaxInterleaveFactor = 4;
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MaxJumpTableSize = 8;
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@ -98,11 +112,6 @@ void AArch64Subtarget::initializeProperties() {
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 8;
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break;
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case Saphira:
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MaxInterleaveFactor = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case Kryo:
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MaxInterleaveFactor = 4;
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VectorInsertExtractBaseCost = 2;
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@ -113,6 +122,11 @@ void AArch64Subtarget::initializeProperties() {
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case Saphira:
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MaxInterleaveFactor = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case ThunderX2T99:
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CacheLineSize = 64;
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PrefFunctionAlignment = 3;
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@ -134,17 +148,6 @@ void AArch64Subtarget::initializeProperties() {
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case CortexA35: break;
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case CortexA53:
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PrefFunctionAlignment = 3;
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break;
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case CortexA55: break;
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case CortexA72:
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case CortexA73:
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case CortexA75:
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PrefFunctionAlignment = 4;
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break;
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case Others: break;
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}
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}
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