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Thumb assembly support for SETEND instruction. 

llvm-svn: 135778
This commit is contained in:
Jim Grosbach 2011-07-22 17:52:23 +00:00
parent 9afae0d01b
commit 39f9388a9d
2 changed files with 11 additions and 16 deletions
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18
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -245,23 +245,13 @@ def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
let Inst{7-0} = val; let Inst{7-0} = val;
} }
def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe", def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
[/* For disassembly only; pattern left blank */]>, []>, T1Encoding<0b101101> {
T1Encoding<0b101101> { bits<1> end;
// A8.6.156 // A8.6.156
let Inst{9-5} = 0b10010; let Inst{9-5} = 0b10010;
let Inst{4} = 1; let Inst{4} = 1;
let Inst{3} = 1; // Big-Endian let Inst{3} = end;
let Inst{2-0} = 0b000;
}
def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101101> {
// A8.6.156
let Inst{9-5} = 0b10010;
let Inst{4} = 1;
let Inst{3} = 0; // Little-Endian
let Inst{2-0} = 0b000; let Inst{2-0} = 0b000;
} }

9
llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -798,8 +798,7 @@ static bool DisassembleThumb1PushPop(MCInst &MI, unsigned Opcode, uint32_t insn,
// tBKPT: imm8 // tBKPT: imm8
// tNOP, tSEV, tYIELD, tWFE, tWFI: // tNOP, tSEV, tYIELD, tWFE, tWFI:
// no operand (except predicate pair) // no operand (except predicate pair)
// tSETENDBE, tSETENDLE, : // tSETEND: i1
// no operand
// Others: tRd tRn // Others: tRd tRn
static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@ -860,6 +859,12 @@ static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn,
return true; return true;
} }
if (Opcode == ARM::tSETEND) {
MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 1)));
NumOpsAdded = 1;
return true;
}
assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
(OpInfo[1].RegClass < 0 || OpInfo[1].RegClass==ARM::tGPRRegClassID) (OpInfo[1].RegClass < 0 || OpInfo[1].RegClass==ARM::tGPRRegClassID)
&& "Expect >=2 operands"); && "Expect >=2 operands");