forked from OSchip/llvm-project
Hexagon: Add support to generate predicated absolute addressing mode
instructions. llvm-svn: 174973
This commit is contained in:
Jyotsna Verma
parent
288604ed0c
commit
39f7a2b7a0
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@ -2237,38 +2237,141 @@ PredicateInstruction(MachineInstr *MI,
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assert (isPredicable(MI) && "Expected predicable instruction");
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bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
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(Cond[0].getImm() == 0));
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MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
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//
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// This assumes that the predicate is always the first operand
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// in the set of inputs.
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//
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MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
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int oper;
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for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
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MachineOperand MO = MI->getOperand(oper);
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if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
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break;
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}
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if (MO.isReg()) {
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MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
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MO.isImplicit(), MO.isKill(),
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MO.isDead(), MO.isUndef(),
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MO.isDebug());
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} else if (MO.isImm()) {
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MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
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} else {
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llvm_unreachable("Unexpected operand type");
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// This will change MI's opcode to its predicate version.
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// However, its operand list is still the old one, i.e. the
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// non-predicate one.
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MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
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int oper = -1;
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unsigned int GAIdx = 0;
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// Indicates whether the current MI has a GlobalAddress operand
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bool hasGAOpnd = false;
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std::vector<MachineOperand> tmpOpnds;
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// Indicates whether we need to shift operands to right.
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bool needShift = true;
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// The predicate is ALWAYS the FIRST input operand !!!
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if (MI->getNumOperands() == 0) {
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// The non-predicate version of MI does not take any operands,
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// i.e. no outs and no ins. In this condition, the predicate
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// operand will be directly placed at Operands[0]. No operand
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// shift is needed.
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// Example: BARRIER
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needShift = false;
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oper = -1;
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}
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else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
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&& MI->getOperand(MI->getNumOperands()-1).isDef()
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&& !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
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// The non-predicate version of MI does not have any input operands.
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// In this condition, we extend the length of Operands[] by one and
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// copy the original last operand to the newly allocated slot.
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// At this moment, it is just a place holder. Later, we will put
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// predicate operand directly into it. No operand shift is needed.
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// Example: r0=BARRIER (this is a faked insn used here for illustration)
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MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
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needShift = false;
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oper = MI->getNumOperands() - 2;
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}
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else {
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// We need to right shift all input operands by one. Duplicate the
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// last operand into the newly allocated slot.
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MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
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}
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if (needShift)
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{
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// Operands[ MI->getNumOperands() - 2 ] has been copied into
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// Operands[ MI->getNumOperands() - 1 ], so we start from
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// Operands[ MI->getNumOperands() - 3 ].
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// oper is a signed int.
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// It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
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for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
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{
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MachineOperand &MO = MI->getOperand(oper);
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// Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
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// <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
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// /\~
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// /||\~
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// ||
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// Predicate Operand here
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if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
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break;
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}
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if (MO.isReg()) {
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MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
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MO.isImplicit(), MO.isKill(),
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MO.isDead(), MO.isUndef(),
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MO.isDebug());
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}
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else if (MO.isImm()) {
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MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
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}
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else if (MO.isGlobal()) {
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// MI can not have more than one GlobalAddress operand.
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assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
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// There is no member function called "ChangeToGlobalAddress" in the
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// MachineOperand class (not like "ChangeToRegister" and
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// "ChangeToImmediate"). So we have to remove them from Operands[] list
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// first, and then add them back after we have inserted the predicate
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// operand. tmpOpnds[] is to remember these operands before we remove
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// them.
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tmpOpnds.push_back(MO);
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// Operands[oper] is a GlobalAddress operand;
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// Operands[oper+1] has been copied into Operands[oper+2];
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hasGAOpnd = true;
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GAIdx = oper;
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continue;
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}
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else {
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assert(false && "Unexpected operand type");
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}
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}
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}
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int regPos = invertJump ? 1 : 0;
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MachineOperand PredMO = Cond[regPos];
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// [oper] now points to the last explicit Def. Predicate operand must be
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// located at [oper+1]. See diagram above.
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// This assumes that the predicate is always the first operand,
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// i.e. Operands[0+numResults], in the set of inputs
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// It is better to have an assert here to check this. But I don't know how
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// to write this assert because findFirstPredOperandIdx() would return -1
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if (oper < -1) oper = -1;
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MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
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PredMO.isImplicit(), PredMO.isKill(),
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PredMO.isDead(), PredMO.isUndef(),
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PredMO.isDebug());
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if (hasGAOpnd)
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{
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unsigned int i;
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// Operands[GAIdx] is the original GlobalAddress operand, which is
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// already copied into tmpOpnds[0].
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// Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
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// Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
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// so we start from [GAIdx+2]
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for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
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tmpOpnds.push_back(MI->getOperand(i));
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// Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
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// It is very important that we always remove from the end of Operands[]
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// MI->getNumOperands() is at least 2 if program goes to here.
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for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
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MI->RemoveOperand(i);
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for (i = 0; i < tmpOpnds.size(); ++i)
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MI->addOperand(tmpOpnds[i]);
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}
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return true;
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}
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@ -0,0 +1,19 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we are able to predicate instructions with abosolute
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; addressing mode.
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; CHECK: if{{ *}}(p{{[0-3]+}}){{ *}}memw(##gvar){{ *}}={{ *}}r{{[0-9]+}}
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@gvar = external global i32
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define i32 @test2(i32 %a, i32 %b) nounwind {
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entry:
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%cmp = icmp eq i32 %a, %b
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @gvar, align 4
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br label %if.end
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if.end:
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ret i32 %b
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}
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