forked from OSchip/llvm-project
Add DAG nodes to represent FP16 <-> FP32 intrinsics
llvm-svn: 98500
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@ -439,6 +439,12 @@ namespace ISD {
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// 5) ISD::CvtCode indicating the type of conversion to do
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// 5) ISD::CvtCode indicating the type of conversion to do
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CONVERT_RNDSAT,
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CONVERT_RNDSAT,
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// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform
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// promotions and truncation for half-precision (16 bit) floating
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// numbers. We need special nodes since FP16 is a storage-only type with
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// special semantics of operations.
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FP16_TO_FP32, FP32_TO_FP16,
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// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
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// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
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// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
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// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
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// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating
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// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating
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@ -4000,6 +4000,14 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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case Intrinsic::pow:
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case Intrinsic::pow:
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visitPow(I);
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visitPow(I);
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return 0;
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return 0;
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case Intrinsic::convert_to_fp16:
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setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
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MVT::i16, getValue(I.getOperand(1))));
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return 0;
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case Intrinsic::convert_from_fp16:
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setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
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MVT::f32, getValue(I.getOperand(1))));
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return 0;
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case Intrinsic::pcmarker: {
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case Intrinsic::pcmarker: {
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SDValue Tmp = getValue(I.getOperand(1));
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SDValue Tmp = getValue(I.getOperand(1));
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DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
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DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
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