forked from OSchip/llvm-project
Expand a bunch of illegal operations on MIPS (found by
inspection and running over CodeGen/Generic). llvm-svn: 76146
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7ecc62d8c1
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@ -83,6 +83,9 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// MIPS doesn't have extending float->double load (?)
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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// Used by legalize types to correctly generate the setcc result.
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// Without this, every float setcc comes with a AND/OR with the result,
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// we don't want this, since the fpcmp result goes to a flag register,
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@ -120,11 +123,20 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FSIN, MVT::f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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setOperationAction(ISD::FPOWI, MVT::f32, Expand);
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setOperationAction(ISD::FPOW, MVT::f32, Expand);
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setOperationAction(ISD::FLOG, MVT::f32, Expand);
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setOperationAction(ISD::FLOG2, MVT::f32, Expand);
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setOperationAction(ISD::FLOG10, MVT::f32, Expand);
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setOperationAction(ISD::FEXP, MVT::f32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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