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TableGen: Produce CoveredBySubRegs summary for register classes 

This will be used in the upcoming "DetectDeadLanes" pass.

llvm-svn: 267850
This commit is contained in:
Matthias Braun 2016-04-28 03:07:11 +00:00
parent cd69bcf6d5
commit 39d1fad554
4 changed files with 12 additions and 3 deletions
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3
llvm/include/llvm/Target/TargetRegisterInfo.h
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@ -70,6 +70,9 @@ public:
const uint8_t AllocationPriority; const uint8_t AllocationPriority;
/// Whether the class supports two (or more) disjunct subregister indices. /// Whether the class supports two (or more) disjunct subregister indices.
const bool HasDisjunctSubRegs; const bool HasDisjunctSubRegs;
/// Whether a combination of subregisters can cover every register in the
/// class. See also the CoveredBySubRegs description in Target.td.
const bool CoveredBySubRegs;
const sc_iterator SuperClasses; const sc_iterator SuperClasses;
ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);

7
llvm/utils/TableGen/CodeGenRegisters.cpp
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@ -1829,11 +1829,14 @@ void CodeGenRegBank::computeDerivedInfo() {
computeRegUnitLaneMasks(); computeRegUnitLaneMasks();
// Compute register class HasDisjunctSubRegs flag. // Compute register class HasDisjunctSubRegs/CoveredBySubRegs flag.
for (CodeGenRegisterClass &RC : RegClasses) { for (CodeGenRegisterClass &RC : RegClasses) {
RC.HasDisjunctSubRegs = false; RC.HasDisjunctSubRegs = false;
for (const CodeGenRegister *Reg : RC.getMembers()) RC.CoveredBySubRegs = true;
for (const CodeGenRegister *Reg : RC.getMembers()) {
RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs;
RC.CoveredBySubRegs &= Reg->CoveredBySubRegs;
}
} }
// Get the weight of each set. // Get the weight of each set.

1
llvm/utils/TableGen/CodeGenRegisters.h
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@ -310,6 +310,7 @@ namespace llvm {
unsigned LaneMask; unsigned LaneMask;
/// True if there are at least 2 subregisters which do not interfere. /// True if there are at least 2 subregisters which do not interfere.
bool HasDisjunctSubRegs; bool HasDisjunctSubRegs;
bool CoveredBySubRegs;
// Return the Record that defined this class, or NULL if the class was // Return the Record that defined this class, or NULL if the class was
// created by TableGen. // created by TableGen.

4
llvm/utils/TableGen/RegisterInfoEmitter.cpp
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@ -1311,7 +1311,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< format("0x%08x,\n ", RC.LaneMask) << format("0x%08x,\n ", RC.LaneMask)
<< (unsigned)RC.AllocationPriority << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
<< (RC.HasDisjunctSubRegs?"true":"false") << (RC.HasDisjunctSubRegs?"true":"false")
<< ", /* HasDisjunctSubRegs */\n "; << ", /* HasDisjunctSubRegs */\n "
<< (RC.CoveredBySubRegs?"true":"false")
<< ", /* CoveredBySubRegs */\n ";
if (RC.getSuperClasses().empty()) if (RC.getSuperClasses().empty())
OS << "NullRegClasses,\n "; OS << "NullRegClasses,\n ";
else else