forked from OSchip/llvm-project
[mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2
Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
This commit is contained in:
Daniel Sanders
parent
94eda2e1ab
commit
39d0051847
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@ -226,7 +226,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM_MM<0x0ec>;
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/// Word Swap Bytes Within Halfwords
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def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>;
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def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
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ISA_MIPS32R2;
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def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
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EXT_FM_MM<0x2c>;
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@ -77,8 +77,6 @@ def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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"true", "Enable vector FPU instructions.">;
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def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
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"Enable 'signext in register' instructions.">;
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def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
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"Enable 'byte/half swap' instructions.">;
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def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
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"Enable 'count leading bits' instructions.">;
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def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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@ -113,7 +111,7 @@ def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips4_32r2, FeatureMips32,
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FeatureSEInReg, FeatureSwap]>;
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FeatureSEInReg]>;
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def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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"Mips32r6",
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"Mips32r6 ISA Support [experimental]",
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@ -218,8 +218,8 @@ def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
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def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
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/// Double Word Swap Bytes/HalfWords
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def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
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def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
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def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
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def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
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def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
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@ -362,10 +362,10 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::CTLZ, MVT::i64, Expand);
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}
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if (!Subtarget->hasSwap()) {
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if (!Subtarget->hasMips32r2())
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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if (!Subtarget->hasMips64r2())
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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}
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if (isGP64bit()) {
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setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
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@ -150,8 +150,6 @@ def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
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AssemblerPredicate<"FeatureSEInReg">;
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def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
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AssemblerPredicate<"FeatureBitCount">;
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def HasSwap : Predicate<"Subtarget.hasSwap()">,
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AssemblerPredicate<"FeatureSwap">;
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def HasMips2 : Predicate<"Subtarget.hasMips2()">,
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AssemblerPredicate<"FeatureMips2">;
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def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
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@ -226,7 +224,6 @@ class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
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// The portions of MIPS-IV that were also added to MIPS32R2
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class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
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class INSN_SWAP { list<Predicate> InsnPredicates = [HasSwap]; }
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class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }
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//===----------------------------------------------------------------------===//
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@ -848,7 +845,7 @@ class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
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// Subword Swap
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class SubwordSwap<string opstr, RegisterOperand RO>:
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InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
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NoItinerary, FrmR, opstr>, INSN_SWAP {
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NoItinerary, FrmR, opstr> {
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let neverHasSideEffects = 1;
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}
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@ -1176,7 +1173,7 @@ def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
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def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
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/// Word Swap Bytes Within Halfwords
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def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
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def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
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/// No operation.
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def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
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@ -81,12 +81,11 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
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IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
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HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips4_32(false),
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HasMips4_32r2(false), HasSEInReg(false), HasSwap(false),
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HasBitCount(false), InMips16Mode(false),
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InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
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HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
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TargetTriple(TT) {
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HasMips4_32r2(false), HasSEInReg(false), HasBitCount(false),
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InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
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AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
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RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
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std::string CPUName = CPU;
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CPUName = selectMipsCPU(TT, CPUName);
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@ -91,9 +91,6 @@ protected:
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// HasSEInReg - SEB and SEH (signext in register) instructions.
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bool HasSEInReg;
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// HasSwap - Byte and half swap instructions.
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bool HasSwap;
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// HasBitCount - Count leading '1' and '0' bits.
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bool HasBitCount;
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@ -215,7 +212,6 @@ public:
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/// Features related to the presence of specific instructions.
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bool hasSEInReg() const { return HasSEInReg; }
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bool hasSwap() const { return HasSwap; }
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bool hasBitCount() const { return HasBitCount; }
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bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
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@ -0,0 +1,10 @@
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# Instructions that are invalid
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#
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \
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# RUN: -mcpu=mips32r2 2>%t1
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# RUN: FileCheck %s < %t1
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.set noat
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dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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