diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index e8015fd062d8..ffe9376d4d41 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -226,7 +226,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM_MM<0x0ec>; /// Word Swap Bytes Within Halfwords - def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>; + def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>, + ISA_MIPS32R2; def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM_MM<0x2c>; diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td index 40f5b938e226..6fe7d26c451a 100644 --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -77,8 +77,6 @@ def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", "true", "Enable vector FPU instructions.">; def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", "Enable 'signext in register' instructions.">; -def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", - "Enable 'byte/half swap' instructions.">; def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", "Enable 'count leading bits' instructions.">; def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", @@ -113,7 +111,7 @@ def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", [FeatureMips4_32r2, FeatureMips32, - FeatureSEInReg, FeatureSwap]>; + FeatureSEInReg]>; def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion", "Mips32r6", "Mips32r6 ISA Support [experimental]", diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 96989cffbe0d..fd8a92729b3f 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -218,8 +218,8 @@ def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>; def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>; /// Double Word Swap Bytes/HalfWords -def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>; -def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>; +def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2; +def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2; def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index ddcbb60ba9a7..92bbd65e23f3 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -362,10 +362,10 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::CTLZ, MVT::i64, Expand); } - if (!Subtarget->hasSwap()) { + if (!Subtarget->hasMips32r2()) setOperationAction(ISD::BSWAP, MVT::i32, Expand); + if (!Subtarget->hasMips64r2()) setOperationAction(ISD::BSWAP, MVT::i64, Expand); - } if (isGP64bit()) { setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 9a3945a7f774..12ebb0c14199 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -150,8 +150,6 @@ def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, AssemblerPredicate<"FeatureSEInReg">; def HasBitCount : Predicate<"Subtarget.hasBitCount()">, AssemblerPredicate<"FeatureBitCount">; -def HasSwap : Predicate<"Subtarget.hasSwap()">, - AssemblerPredicate<"FeatureSwap">; def HasMips2 : Predicate<"Subtarget.hasMips2()">, AssemblerPredicate<"FeatureMips2">; def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">, @@ -226,7 +224,6 @@ class INSN_MIPS4_32 { list InsnPredicates = [HasMips4_32]; } // The portions of MIPS-IV that were also added to MIPS32R2 class INSN_MIPS4_32R2 { list InsnPredicates = [HasMips4_32r2]; } -class INSN_SWAP { list InsnPredicates = [HasSwap]; } class INSN_SEINREG { list InsnPredicates = [HasSEInReg]; } //===----------------------------------------------------------------------===// @@ -848,7 +845,7 @@ class SignExtInReg: InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], - NoItinerary, FrmR, opstr>, INSN_SWAP { + NoItinerary, FrmR, opstr> { let neverHasSideEffects = 1; } @@ -1176,7 +1173,7 @@ def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; /// Word Swap Bytes Within Halfwords -def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; +def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2; /// No operation. def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index b19ef6526411..1913d895b74d 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -81,12 +81,11 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips4_32(false), - HasMips4_32r2(false), HasSEInReg(false), HasSwap(false), - HasBitCount(false), InMips16Mode(false), - InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), - HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), - HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM), - TargetTriple(TT) { + HasMips4_32r2(false), HasSEInReg(false), HasBitCount(false), + InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), + InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), + AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), + RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) { std::string CPUName = CPU; CPUName = selectMipsCPU(TT, CPUName); diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h index aa69110e4479..dba4aede2ede 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.h +++ b/llvm/lib/Target/Mips/MipsSubtarget.h @@ -91,9 +91,6 @@ protected: // HasSEInReg - SEB and SEH (signext in register) instructions. bool HasSEInReg; - // HasSwap - Byte and half swap instructions. - bool HasSwap; - // HasBitCount - Count leading '1' and '0' bits. bool HasBitCount; @@ -215,7 +212,6 @@ public: /// Features related to the presence of specific instructions. bool hasSEInReg() const { return HasSEInReg; } - bool hasSwap() const { return HasSwap; } bool hasBitCount() const { return HasBitCount; } bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } diff --git a/llvm/test/MC/Mips/mips32r2/invalid-mips64r2.s b/llvm/test/MC/Mips/mips32r2/invalid-mips64r2.s new file mode 100644 index 000000000000..293e58eaed35 --- /dev/null +++ b/llvm/test/MC/Mips/mips32r2/invalid-mips64r2.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \ +# RUN: -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +