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[X86] Add a stub for Intel's alderlake. 

No scheduling, no autodetection.
This commit is contained in:
Benjamin Kramer 2020-10-24 18:00:33 +02:00
parent bd2cf96c09
commit 39a0d6889d
14 changed files with 124 additions and 6 deletions
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3
clang/docs/ReleaseNotes.rst
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@ -190,7 +190,8 @@ X86 Support in Clang
- The x86 intrinsics ``__rorb``, ``__rorw``, ``__rord``, ``__rorq`, ``_rotr``,
``_rotwr`` and ``_lrotr`` may now be used within constant expressions.
- Support for ``-march=sapphirerapids`` was added.
- Support for ``-march=alderlake``, ``-march=sapphirerapids`` and
``-march=znver3`` was added.
- Support for ``-march=x86-64-v[234]`` has been added.
See :doc:`UsersManual` for details about these micro-architecture levels.

2
clang/lib/Basic/Targets/X86.cpp
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@ -468,6 +468,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_IcelakeServer:
case CK_Tigerlake:
case CK_SapphireRapids:
case CK_Alderlake:
// FIXME: Historically, we defined this legacy name, it would be nice to
// remove it at some point. We've never exposed fine-grained names for
// recent primary x86 CPUs, and we should keep it that way.
@ -1308,6 +1309,7 @@ Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_SapphireRapids:
case CK_IcelakeClient:
case CK_IcelakeServer:
case CK_Alderlake:
case CK_KNL:
case CK_KNM:
// K7

3
clang/test/CodeGen/attr-target-mv.c
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@ -12,6 +12,7 @@ int __attribute__((target("arch=icelake-server"))) foo(void) {return 7;}
int __attribute__((target("arch=cooperlake"))) foo(void) {return 8;}
int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;}
int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;}
int __attribute__((target("arch=alderlake"))) foo(void) {return 11;}
int __attribute__((target("default"))) foo(void) { return 2; }
int bar() {
@ -94,6 +95,8 @@ __attribute__((target("avx,sse4.2"), used)) inline void foo_used2(int i, double
// LINUX: ret i32 9
// LINUX: define i32 @foo.arch_sapphirerapids()
// LINUX: ret i32 10
// LINUX: define i32 @foo.arch_alderlake()
// LINUX: ret i32 11
// LINUX: define i32 @foo()
// LINUX: ret i32 2
// LINUX: define i32 @bar()

1
clang/test/CodeGen/target-builtin-noerror.c
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@ -85,6 +85,7 @@ void verifyfeaturestrings() {
}
void verifycpustrings() {
(void)__builtin_cpu_is("alderlake");
(void)__builtin_cpu_is("amd");
(void)__builtin_cpu_is("amdfam10h");
(void)__builtin_cpu_is("amdfam15h");

4
clang/test/Driver/x86-march.c
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@ -80,6 +80,10 @@
// RUN: | FileCheck %s -check-prefix=tigerlake
// tigerlake: "-target-cpu" "tigerlake"
//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=alderlake 2>&1 \
// RUN: | FileCheck %s -check-prefix=alderlake
// alderlake: "-target-cpu" "alderlake"
//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=lakemont 2>&1 \
// RUN: | FileCheck %s -check-prefix=lakemont
// lakemont: "-target-cpu" "lakemont"

8
clang/test/Misc/target-invalid-cpu-note.c
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@ -21,7 +21,7 @@
// X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
// X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
// X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, lakemont, k6, k6-2, k6-3,
// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
// X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
// X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
// X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,
@ -33,7 +33,7 @@
// X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere,
// X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell,
// X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake,
// X86_64-SAME: icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
// X86_64-SAME: icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
// X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1,
// X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,
// X86_64-SAME: x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}}
@ -46,7 +46,7 @@
// TUNE_X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
// TUNE_X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
// TUNE_X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, lakemont, k6, k6-2, k6-3,
// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
// TUNE_X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
// TUNE_X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
// TUNE_X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,
@ -60,7 +60,7 @@
// TUNE_X86_64-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
// TUNE_X86_64-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
// TUNE_X86_64-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, lakemont, k6, k6-2, k6-3,
// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
// TUNE_X86_64-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
// TUNE_X86_64-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
// TUNE_X86_64-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,

85
clang/test/Preprocessor/predefined-arch-macros.c
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@ -1775,6 +1775,91 @@
// CHECK_SPR_M64: #define __x86_64 1
// CHECK_SPR_M64: #define __x86_64__ 1
// RUN: %clang -march=alderlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ADL_M32
// CHECK_ADL_M32: #define __ADX__ 1
// CHECK_ADL_M32: #define __AES__ 1
// CHECK_ADL_M32: #define __AVX2__ 1
// CHECK_ADL_M32-NOT: AVX512
// CHECK_ADL_M32: #define __AVX__ 1
// CHECK_ADL_M32: #define __BMI2__ 1
// CHECK_ADL_M32: #define __BMI__ 1
// CHECK_ADL_M32: #define __CLDEMOTE__ 1
// CHECK_ADL_M32: #define __CLFLUSHOPT__ 1
// CHECK_ADL_M32: #define __F16C__ 1
// CHECK_ADL_M32: #define __FMA__ 1
// CHECK_ADL_M32: #define __HRESET__ 1
// CHECK_ADL_M32: #define __INVPCID__ 1
// CHECK_ADL_M32: #define __LZCNT__ 1
// CHECK_ADL_M32: #define __MMX__ 1
// CHECK_ADL_M32: #define __MOVBE__ 1
// CHECK_ADL_M32: #define __PCLMUL__ 1
// CHECK_ADL_M32: #define __POPCNT__ 1
// CHECK_ADL_M32: #define __PRFCHW__ 1
// CHECK_ADL_M32: #define __PTWRITE__ 1
// CHECK_ADL_M32: #define __RDRND__ 1
// CHECK_ADL_M32: #define __RDSEED__ 1
// CHECK_ADL_M32: #define __SERIALIZE__ 1
// CHECK_ADL_M32: #define __SGX__ 1
// CHECK_ADL_M32: #define __SSE2__ 1
// CHECK_ADL_M32: #define __SSE3__ 1
// CHECK_ADL_M32: #define __SSE4_1__ 1
// CHECK_ADL_M32: #define __SSE4_2__ 1
// CHECK_ADL_M32: #define __SSE__ 1
// CHECK_ADL_M32: #define __SSSE3__ 1
// CHECK_ADL_M32: #define __WAITPKG__ 1
// CHECK_ADL_M32: #define __XSAVEC__ 1
// CHECK_ADL_M32: #define __XSAVEOPT__ 1
// CHECK_ADL_M32: #define __XSAVES__ 1
// CHECK_ADL_M32: #define __XSAVE__ 1
// CHECK_ADL_M32: #define i386 1
// RUN: %clang -march=alderlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ADL_M64
// CHECK_ADL_M64: #define __ADX__ 1
// CHECK_ADL_M64: #define __AES__ 1
// CHECK_ADL_M64: #define __AVX2__ 1
// CHECK_ADL_M64-NOT: AVX512
// CHECK_ADL_M64: #define __AVX__ 1
// CHECK_ADL_M64: #define __BMI2__ 1
// CHECK_ADL_M64: #define __BMI__ 1
// CHECK_ADL_M64: #define __CLDEMOTE__ 1
// CHECK_ADL_M64: #define __CLFLUSHOPT__ 1
// CHECK_ADL_M64: #define __F16C__ 1
// CHECK_ADL_M64: #define __FMA__ 1
// CHECK_ADL_M64: #define __HRESET__ 1
// CHECK_ADL_M64: #define __INVPCID__ 1
// CHECK_ADL_M64: #define __LZCNT__ 1
// CHECK_ADL_M64: #define __MMX__ 1
// CHECK_ADL_M64: #define __MOVBE__ 1
// CHECK_ADL_M64: #define __PCLMUL__ 1
// CHECK_ADL_M64: #define __POPCNT__ 1
// CHECK_ADL_M64: #define __PRFCHW__ 1
// CHECK_ADL_M64: #define __PTWRITE__ 1
// CHECK_ADL_M64: #define __RDRND__ 1
// CHECK_ADL_M64: #define __RDSEED__ 1
// CHECK_ADL_M64: #define __SERIALIZE__ 1
// CHECK_ADL_M64: #define __SGX__ 1
// CHECK_ADL_M64: #define __SSE2_MATH__ 1
// CHECK_ADL_M64: #define __SSE2__ 1
// CHECK_ADL_M64: #define __SSE3__ 1
// CHECK_ADL_M64: #define __SSE4_1__ 1
// CHECK_ADL_M64: #define __SSE4_2__ 1
// CHECK_ADL_M64: #define __SSE_MATH__ 1
// CHECK_ADL_M64: #define __SSE__ 1
// CHECK_ADL_M64: #define __SSSE3__ 1
// CHECK_ADL_M64: #define __WAITPKG__ 1
// CHECK_ADL_M64: #define __XSAVEC__ 1
// CHECK_ADL_M64: #define __XSAVEOPT__ 1
// CHECK_ADL_M64: #define __XSAVES__ 1
// CHECK_ADL_M64: #define __XSAVE__ 1
// CHECK_ADL_M64: #define __amd64 1
// CHECK_ADL_M64: #define __amd64__ 1
// CHECK_ADL_M64: #define __x86_64 1
// CHECK_ADL_M64: #define __x86_64__ 1
// RUN: %clang -march=atom -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M32

1
compiler-rt/lib/builtins/cpu_model.c
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@ -85,6 +85,7 @@ enum ProcessorSubtypes {
INTEL_COREI7_TIGERLAKE,
INTEL_COREI7_COOPERLAKE,
INTEL_COREI7_SAPPHIRERAPIDS,
INTEL_COREI7_ALDERLAKE,
CPU_SUBTYPE_MAX
};

3
llvm/docs/ReleaseNotes.rst
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@ -109,7 +109,8 @@ During this release ...
* The 'mpx' feature was removed from the backend. It had been removed from clang
frontend in 10.0. Mention of the 'mpx' feature in an IR file will print a
message to stderr, but IR should still compile.
* Support for ``-march=sapphirerapids`` and ``-march=x86-64-v[234]`` has been added.
* Support for ``-march=alderlake``, ``-march=sapphirerapids``,
``-march=znver3`` and ``-march=x86-64-v[234]`` has been added.
* The assembler now has support for {disp32} and {disp8} pseudo prefixes for
controlling displacement size for memory operands and jump displacements. The
assembler also supports the .d32 and .d8 mnemonic suffixes to do the same.

1
llvm/include/llvm/Support/X86TargetParser.def
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@ -85,6 +85,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_CASCADELAKE, "cascadelake")
X86_CPU_SUBTYPE(INTEL_COREI7_TIGERLAKE, "tigerlake")
X86_CPU_SUBTYPE(INTEL_COREI7_COOPERLAKE, "cooperlake")
X86_CPU_SUBTYPE(INTEL_COREI7_SAPPHIRERAPIDS, "sapphirerapids")
X86_CPU_SUBTYPE(INTEL_COREI7_ALDERLAKE, "alderlake")
#undef X86_CPU_SUBTYPE

1
llvm/include/llvm/Support/X86TargetParser.h
View File

@ -101,6 +101,7 @@ enum CPUKind {
CK_IcelakeServer,
CK_Tigerlake,
CK_SapphireRapids,
CK_Alderlake,
CK_KNL,
CK_KNM,
CK_Lakemont,

5
llvm/lib/Support/X86TargetParser.cpp
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@ -206,6 +206,9 @@ constexpr FeatureBitset FeaturesSapphireRapids =
FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
FeatureWAITPKG;
constexpr FeatureBitset FeaturesAlderlake =
FeaturesSkylakeClient | FeatureCLDEMOTE | FeatureHRESET | FeaturePTWRITE |
FeatureSERIALIZE | FeatureWAITPKG;
// Intel Atom processors.
// Bonnell has feature parity with Core2 and adds MOVBE.
@ -357,6 +360,8 @@ constexpr ProcInfo Processors[] = {
{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
// Sapphire Rapids microarchitecture based processors.
{ {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
// Alderlake microarchitecture based processors.
{ {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
// Knights Landing processor.
{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
// Knights Mill processor.

12
llvm/lib/Target/X86/X86.td
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@ -780,6 +780,16 @@ def ProcessorFeatures {
list<SubtargetFeature> SPRFeatures =
!listconcat(ICXFeatures, SPRAdditionalFeatures);
// Alderlake
list<SubtargetFeature> ADLAdditionalFeatures = [FeatureCLDEMOTE,
FeatureHRESET,
FeaturePTWRITE,
FeatureSERIALIZE,
FeatureWAITPKG];
list<SubtargetFeature> ADLTuning = SKLTuning;
list<SubtargetFeature> ADLFeatures =
!listconcat(SKLFeatures, ADLAdditionalFeatures);
// Atom
list<SubtargetFeature> AtomFeatures = [FeatureX87,
FeatureCMPXCHG8B,
@ -1281,6 +1291,8 @@ def : ProcModel<"tigerlake", SkylakeServerModel,
ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
def : ProcModel<"sapphirerapids", SkylakeServerModel,
ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
def : ProcModel<"alderlake", SkylakeClientModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
// AMD CPUs.

1
llvm/test/CodeGen/X86/cpus-intel.ll
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@ -41,6 +41,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=alderlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=atom 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty