forked from OSchip/llvm-project
parent
3c4f04112a
commit
3974a80307
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@ -1612,7 +1612,7 @@ def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero),
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def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
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Pseudo, NoItinerary,
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"mcr", "\tp15, 0, $zero, c7, c10, 5",
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"mcr", "\tp15, 0, $zero, c7, c10, 4",
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[(ARMSyncBarrierV6 GPR:$zero)]>,
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Requires<[IsARM, HasV6]> {
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// FIXME: add support for options other than a full system DSB
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