forked from OSchip/llvm-project
[X86] Use update_llc_test_checks.py to re-generate a test in preparation for an upcoming commit. NFC
llvm-svn: 271234
This commit is contained in:
Craig Topper
parent
29ce55df5a
commit
39716f8358
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@ -1,7 +1,11 @@
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; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx2 | FileCheck %s
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define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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; CHECK: vpblendw
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; CHECK-LABEL: test_x86_avx2_pblendw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
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; CHECK-NEXT: retl
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 7) ; <<16 x i16>> [#uses=1]
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ret <16 x i16> %res
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}
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@ -9,7 +13,10 @@ declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32) nounwind
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define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK: vpblendd
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; CHECK-LABEL: test_x86_avx2_pblendd_128:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
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; CHECK-NEXT: retl
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 7) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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@ -17,7 +24,10 @@ declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32) nounwind
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define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
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; CHECK: vpblendd
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; CHECK-LABEL: test_x86_avx2_pblendd_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
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; CHECK-NEXT: retl
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 7) ; <<8 x i32>> [#uses=1]
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ret <8 x i32> %res
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}
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@ -25,7 +35,10 @@ declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32) nounwind
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define <16 x i16> @test_x86_avx2_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) {
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; CHECK: vmpsadbw
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; CHECK-LABEL: test_x86_avx2_mpsadbw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i32 7) ; <<16 x i16>> [#uses=1]
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ret <16 x i16> %res
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}
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@ -33,7 +46,10 @@ declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i32) nounwind re
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define <4 x i64> @test_x86_avx2_psll_dq_bs(<4 x i64> %a0) {
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; CHECK: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
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; CHECK-LABEL: test_x86_avx2_psll_dq_bs:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -41,7 +57,10 @@ declare <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64>, i32) nounwind readnone
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define <4 x i64> @test_x86_avx2_psrl_dq_bs(<4 x i64> %a0) {
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; CHECK: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
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; CHECK-LABEL: test_x86_avx2_psrl_dq_bs:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -49,7 +68,10 @@ declare <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64>, i32) nounwind readnone
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define <4 x i64> @test_x86_avx2_psll_dq(<4 x i64> %a0) {
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; CHECK: vpslldq {{.*#+}} ymm0 = zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
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; CHECK-LABEL: test_x86_avx2_psll_dq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -57,7 +79,10 @@ declare <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64>, i32) nounwind readnone
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define <4 x i64> @test_x86_avx2_psrl_dq(<4 x i64> %a0) {
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; CHECK: vpsrldq {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero
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; CHECK-LABEL: test_x86_avx2_psrl_dq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -65,8 +90,11 @@ declare <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64>, i32) nounwind readnone
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define <2 x i64> @test_x86_avx2_vextracti128(<4 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx2_vextracti128:
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; CHECK: vextracti128
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; CHECK-LABEL: test_x86_avx2_vextracti128:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retl
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%res = call <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64> %a0, i8 7)
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ret <2 x i64> %res
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@ -75,8 +103,10 @@ declare <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64>, i8) nounwind readnone
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define <4 x i64> @test_x86_avx2_vinserti128(<4 x i64> %a0, <2 x i64> %a1) {
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; CHECK-LABEL: test_x86_avx2_vinserti128:
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; CHECK: vinserti128
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; CHECK-LABEL: test_x86_avx2_vinserti128:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64> %a0, <2 x i64> %a1, i8 7)
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ret <4 x i64> %res
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@ -85,10 +115,10 @@ declare <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64>, <2 x i64>, i8) nounwind
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define <4 x double> @test_x86_avx2_vbroadcast_sd_pd_256(<2 x double> %a0) {
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; CHECK-LABEL: test_x86_avx2_vbroadcast_sd_pd_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
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; CHECK-NEXT: retl
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; CHECK-LABEL: test_x86_avx2_vbroadcast_sd_pd_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <4 x double> @llvm.x86.avx2.vbroadcast.sd.pd.256(<2 x double> %a0)
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ret <4 x double> %res
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}
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@ -96,10 +126,10 @@ declare <4 x double> @llvm.x86.avx2.vbroadcast.sd.pd.256(<2 x double>) nounwind
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define <4 x float> @test_x86_avx2_vbroadcast_ss_ps(<4 x float> %a0) {
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; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
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; CHECK-NEXT: retl
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; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.avx2.vbroadcast.ss.ps(<4 x float> %a0)
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ret <4 x float> %res
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}
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@ -107,10 +137,10 @@ declare <4 x float> @llvm.x86.avx2.vbroadcast.ss.ps(<4 x float>) nounwind readon
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define <8 x float> @test_x86_avx2_vbroadcast_ss_ps_256(<4 x float> %a0) {
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; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
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; CHECK-NEXT: retl
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; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <8 x float> @llvm.x86.avx2.vbroadcast.ss.ps.256(<4 x float> %a0)
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ret <8 x float> %res
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}
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@ -206,7 +236,10 @@ declare <4 x i64> @llvm.x86.avx2.pbroadcastq.256(<2 x i64>) nounwind readonly
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define <8 x i32> @test_x86_avx2_pmovsxbd(<16 x i8> %a0) {
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; CHECK: vpmovsxbd
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; CHECK-LABEL: test_x86_avx2_pmovsxbd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbd %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %a0) ; <<8 x i32>> [#uses=1]
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ret <8 x i32> %res
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}
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@ -214,7 +247,10 @@ declare <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8>) nounwind readnone
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define <4 x i64> @test_x86_avx2_pmovsxbq(<16 x i8> %a0) {
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; CHECK: vpmovsxbq
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; CHECK-LABEL: test_x86_avx2_pmovsxbq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbq %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %a0) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -222,7 +258,10 @@ declare <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8>) nounwind readnone
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define <16 x i16> @test_x86_avx2_pmovsxbw(<16 x i8> %a0) {
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; CHECK: vpmovsxbw
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; CHECK-LABEL: test_x86_avx2_pmovsxbw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
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ret <16 x i16> %res
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}
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@ -230,7 +269,10 @@ declare <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8>) nounwind readnone
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define <4 x i64> @test_x86_avx2_pmovsxdq(<4 x i32> %a0) {
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; CHECK: vpmovsxdq
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; CHECK-LABEL: test_x86_avx2_pmovsxdq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %a0) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -238,7 +280,10 @@ declare <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32>) nounwind readnone
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define <8 x i32> @test_x86_avx2_pmovsxwd(<8 x i16> %a0) {
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; CHECK: vpmovsxwd
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; CHECK-LABEL: test_x86_avx2_pmovsxwd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %a0) ; <<8 x i32>> [#uses=1]
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ret <8 x i32> %res
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}
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@ -246,7 +291,10 @@ declare <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16>) nounwind readnone
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define <4 x i64> @test_x86_avx2_pmovsxwq(<8 x i16> %a0) {
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; CHECK: vpmovsxwq
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; CHECK-LABEL: test_x86_avx2_pmovsxwq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwq %xmm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %a0) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -254,7 +302,10 @@ declare <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16>) nounwind readnone
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define <8 x i32> @test_x86_avx2_pmovzxbd(<16 x i8> %a0) {
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; CHECK: vpmovzxbd
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; CHECK-LABEL: test_x86_avx2_pmovzxbd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
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; CHECK-NEXT: retl
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%res = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %a0) ; <<8 x i32>> [#uses=1]
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ret <8 x i32> %res
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}
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@ -262,7 +313,10 @@ declare <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8>) nounwind readnone
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define <4 x i64> @test_x86_avx2_pmovzxbq(<16 x i8> %a0) {
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; CHECK: vpmovzxbq
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; CHECK-LABEL: test_x86_avx2_pmovzxbq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: retl
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%res = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %a0) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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@ -270,7 +324,10 @@ declare <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8>) nounwind readnone
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define <16 x i16> @test_x86_avx2_pmovzxbw(<16 x i8> %a0) {
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; CHECK: vpmovzxbw
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; CHECK-LABEL: test_x86_avx2_pmovzxbw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; CHECK-NEXT: retl
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%res = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %a0) ; <<16 x i16>> [#uses=1]
|
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ret <16 x i16> %res
|
||||
}
|
||||
|
|
@ -278,7 +335,10 @@ declare <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8>) nounwind readnone
|
|||
|
||||
|
||||
define <4 x i64> @test_x86_avx2_pmovzxdq(<4 x i32> %a0) {
|
||||
; CHECK: vpmovzxdq
|
||||
; CHECK-LABEL: test_x86_avx2_pmovzxdq:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
|
||||
; CHECK-NEXT: retl
|
||||
%res = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %a0) ; <<4 x i64>> [#uses=1]
|
||||
ret <4 x i64> %res
|
||||
}
|
||||
|
|
@ -286,7 +346,10 @@ declare <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32>) nounwind readnone
|
|||
|
||||
|
||||
define <8 x i32> @test_x86_avx2_pmovzxwd(<8 x i16> %a0) {
|
||||
; CHECK: vpmovzxwd
|
||||
; CHECK-LABEL: test_x86_avx2_pmovzxwd:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; CHECK-NEXT: retl
|
||||
%res = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %a0) ; <<8 x i32>> [#uses=1]
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
|
|
@ -294,7 +357,10 @@ declare <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16>) nounwind readnone
|
|||
|
||||
|
||||
define <4 x i64> @test_x86_avx2_pmovzxwq(<8 x i16> %a0) {
|
||||
; CHECK: vpmovzxwq
|
||||
; CHECK-LABEL: test_x86_avx2_pmovzxwq:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
|
||||
; CHECK-NEXT: retl
|
||||
%res = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %a0) ; <<4 x i64>> [#uses=1]
|
||||
ret <4 x i64> %res
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue