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[mips] Correct the predicates of arithmetic and logic instructions. 

As part of this effort, duplicate and correct the predicates of some
aliases. Also disable code generation of some short form instructions
for FastISel, as it would otherwise reject them.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D47075

llvm-svn: 333530
This commit is contained in:
Simon Dardis 2018-05-30 11:33:35 +00:00
parent 690a99a5fb
commit 39710e3555
8 changed files with 93 additions and 50 deletions
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12
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -1681,6 +1681,18 @@ def : MipsInstAlias<"not $rt, $rs",
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"neg $rt, $rs",
(SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"neg $rt",
(SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"negu $rt, $rs",
(SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"negu $rt",
(SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32R6;
//===----------------------------------------------------------------------===//
//

96
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -610,25 +610,31 @@ class MtCop0MM<string opstr, RegisterOperand DstRC,
let BaseOpcode = opstr;
}
def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
let FastISelShouldIgnore = 1 in {
def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
}
def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
ISA_MICROMIPS_NOT_32R6;
ISA_MICROMIPS_NOT_32R6;
def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
ISA_MICROMIPS_NOT_32R6;
def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
ISA_MICROMIPS_NOT_32R6;
ISA_MICROMIPS_NOT_32R6;
let FastISelShouldIgnore = 1 in
def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
ISA_MICROMIPS_NOT_32R6;
def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
let FastISelShouldIgnore = 1 in {
def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
}
def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
@ -705,56 +711,60 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6,
def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
COMPACT_BRANCH_FM_MM<0x5>;
}
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
let DecoderNamespace = "MicroMips" in {
/// Arithmetic Instructions (ALU Immediate)
def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
ADDI_FM_MM<0xc>;
ADDI_FM_MM<0xc>, ISA_MICROMIPS32_NOT_MIPS32R6;
def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
ADDI_FM_MM<0x4>;
ADDI_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
SLTI_FM_MM<0x24>;
SLTI_FM_MM<0x24>, ISA_MICROMIPS;
def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
SLTI_FM_MM<0x2c>;
SLTI_FM_MM<0x2c>, ISA_MICROMIPS;
def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
ADDI_FM_MM<0x34>;
ADDI_FM_MM<0x34>, ISA_MICROMIPS32_NOT_MIPS32R6;
def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
or>, ADDI_FM_MM<0x14>;
or>, ADDI_FM_MM<0x14>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
immZExt16, xor>, ADDI_FM_MM<0x1c>;
def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM;
immZExt16, xor>, ADDI_FM_MM<0x1c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM,
ISA_MICROMIPS32_NOT_MIPS32R6;
def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
LW_FM_MM<0xc>;
/// Arithmetic Instructions (3-Operand, R-Type)
def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
ADD_FM_MM<0, 0x150>;
ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
ADD_FM_MM<0, 0x1d0>;
ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>,
ADD_FM_MM<0, 0x210>;
ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;
def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
ADD_FM_MM<0, 0x110>;
ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
ADD_FM_MM<0, 0x190>;
def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
ADD_FM_MM<0, 0x190>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>,
ISA_MICROMIPS;
def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
ADD_FM_MM<0, 0x390>;
ADD_FM_MM<0, 0x390>, ISA_MICROMIPS;
def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
ADD_FM_MM<0, 0x250>;
ADD_FM_MM<0, 0x250>, ISA_MICROMIPS32_NOT_MIPS32R6;
def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
ADD_FM_MM<0, 0x290>;
ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6;
def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
ADD_FM_MM<0, 0x310>;
ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6;
def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x22c>;
MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x26c>;
MULT_FM_MM<0x26c>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x2ac>, ISA_MIPS1_NOT_32R6_64R6;
MULT_FM_MM<0x2ac>, ISA_MICROMIPS32_NOT_MIPS32R6;
def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x2ec>, ISA_MIPS1_NOT_32R6_64R6;
MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Arithmetic Instructions with PC and Immediate
def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
@ -773,12 +783,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS;
def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
SRA_FM_MM<0xc0, 0> {
SRA_FM_MM<0xc0, 0>, ISA_MICROMIPS {
list<dag> Pattern = [(set GPR32Opnd:$rd,
(rotr GPR32Opnd:$rt, immZExt5:$shamt))];
}
def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
SRLV_FM_MM<0xd0, 0> {
SRLV_FM_MM<0xd0, 0>, ISA_MICROMIPS {
list<dag> Pattern = [(set GPR32Opnd:$rd,
(rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
}
@ -1266,6 +1276,18 @@ let Predicates = [InMicroMips] in {
def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"neg $rt, $rs",
(SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"neg $rt",
(SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"negu $rt, $rs",
(SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"negu $rt",
(SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tge $rs, $rt",

16
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -2608,15 +2608,15 @@ def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
}
def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>,
ISA_MIPS32;
def : MipsInstAlias<"neg $rt, $rs",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"neg $rt",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
def : MipsInstAlias<"negu $rt, $rs",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"neg $rt, $rs",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"neg $rt",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
def : MipsInstAlias<"negu $rt, $rs",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
def : MipsInstAlias<
"sgt $rd, $rs, $rt",
(SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;

4
llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
View File

@ -62,8 +62,8 @@
0xa0 0x43 0xe2 0xff # CHECK: bc1t -56
0xe6 0x00 0x90 0x49 # CHECK: sub $9, $6, $7
0xa3 0x00 0xd0 0x21 # CHECK: subu $4, $3, $5
0xe0 0x00 0x90 0x31 # CHECK: sub $6, $zero, $7
0xe0 0x00 0xd0 0x31 # CHECK: subu $6, $zero, $7
0xe0 0x00 0x90 0x31 # CHECK: neg $6, $7
0xe0 0x00 0xd0 0x31 # CHECK: negu $6, $7
0x08 0x00 0x50 0x39 # CHECK: addu $7, $8, $zero
0xa3 0x00 0x50 0x1b # CHECK: slt $3, $3, $5
0x63 0x90 0x67 0x00 # CHECK: slti $3, $3, 103

4
llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
View File

@ -62,8 +62,8 @@
0x43 0xa0 0xff 0xe2 # CHECK: bc1t -56
0x00 0xe6 0x49 0x90 # CHECK: sub $9, $6, $7
0x00 0xa3 0x21 0xd0 # CHECK: subu $4, $3, $5
0x00 0xe0 0x31 0x90 # CHECK: sub $6, $zero, $7
0x00 0xe0 0x31 0xd0 # CHECK: subu $6, $zero, $7
0x00 0xe0 0x31 0x90 # CHECK: neg $6, $7
0x00 0xe0 0x31 0xd0 # CHECK: negu $6, $7
0x00 0x08 0x39 0x50 # CHECK: addu $7, $8, $zero
0x00 0xa3 0x1b 0x50 # CHECK: slt $3, $3, $5
0x90 0x63 0x00 0x67 # CHECK: slti $3, $3, 103

5
llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
View File

@ -355,3 +355,8 @@
0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
0x00 0xa0 0x21 0x90 # CHECK: neg $4, $5
0x00 0x80 0x21 0x90 # CHECK: neg $4, $4
0x00 0xa0 0x21 0xd0 # CHECK: negu $4, $5
0x00 0x80 0x21 0xd0 # CHECK: negu $4, $4

2
llvm/test/MC/Mips/micromips/valid.s
View File

@ -70,7 +70,7 @@ subu $4, $3, $5 # CHECK: subu $4, $3, $5 # encoding: [0x00,0x
sub $6, $zero, $7 # CHECK: neg $6, $7 # encoding: [0x00,0xe0,0x31,0x90]
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x70]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D32_MM
subu $6, $zero, $7 # CHECK: subu $6, $zero, $7 # encoding: [0x00,0xe0,0x31,0xd0]
subu $6, $zero, $7 # CHECK: negu $6, $7 # encoding: [0x00,0xe0,0x31,0xd0]
addu $7, $8, $zero # CHECK: addu $7, $8, $zero # encoding: [0x00,0x08,0x39,0x50]
slt $3, $3, $5 # CHECK: slt $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x50]
slti $3, $3, 103 # CHECK: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67]

4
llvm/test/MC/Mips/micromips32r6/valid.s
View File

@ -400,3 +400,7 @@
blezc $2, 256 # CHECK: blezc $2, 256 # encoding: [0xf4,0x40,0x00,0x40]
bgezc $16, 512 # CHECK: bgezc $16, 512 # encoding: [0xf6,0x10,0x00,0x80]
bgtzc $12, 1024 # CHECK: bgtzc $12, 1024 # encoding: [0xd5,0x80,0x01,0x00]
neg $4, $5 # CHECK: neg $4, $5 # encoding: [0x00,0xa0,0x21,0x90]
neg $4, $4 # CHECK: neg $4, $4 # encoding: [0x00,0x80,0x21,0x90]
negu $4, $5 # CHECK: negu $4, $5 # encoding: [0x00,0xa0,0x21,0xd0]
negu $4, $4 # CHECK: negu $4, $4 # encoding: [0x00,0x80,0x21,0xd0]