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[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC 

We fold integer setcc into SELECT_CC during DAG combine even if
the SELECT_CC has FP result type, but we had no test coverage.
This commit is contained in:
Craig Topper 2022-08-16 21:23:09 -07:00
parent 9fc65658f5
commit 39707c1a9a
3 changed files with 406 additions and 0 deletions
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136
llvm/test/CodeGen/RISCV/double-select-icmp.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32d | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: -target-abi=lp64d | FileCheck %s
define double @select_icmp_eq(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_eq:
; CHECK: # %bb.0:
; CHECK-NEXT: beq a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_ne(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_ne:
; CHECK: # %bb.0:
; CHECK-NEXT: bne a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_ugt(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_ugt:
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a1, a0, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_uge:
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_ult:
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_ule:
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_sgt:
; CHECK: # %bb.0:
; CHECK-NEXT: blt a1, a0, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_sge:
; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_slt:
; CHECK: # %bb.0:
; CHECK-NEXT: blt a0, a1, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_sle:
; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}

135
llvm/test/CodeGen/RISCV/float-select-icmp.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck %s
define float @select_icmp_eq(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_eq:
; CHECK: # %bb.0:
; CHECK-NEXT: beq a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ne(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_ne:
; CHECK: # %bb.0:
; CHECK-NEXT: bne a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ugt(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_ugt:
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a1, a0, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_uge(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_uge:
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ult(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_ult:
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ule(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_ule:
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_sgt(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_sgt:
; CHECK: # %bb.0:
; CHECK-NEXT: blt a1, a0, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_sge(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_sge:
; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_slt(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_slt:
; CHECK: # %bb.0:
; CHECK-NEXT: blt a0, a1, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_sle(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_sle:
; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}

135
llvm/test/CodeGen/RISCV/half-select-icmp.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck %s
define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_eq:
; CHECK: # %bb.0:
; CHECK-NEXT: beq a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_ne:
; CHECK: # %bb.0:
; CHECK-NEXT: bne a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_ugt:
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a1, a0, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_uge:
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_ult:
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_ule:
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_sgt:
; CHECK: # %bb.0:
; CHECK-NEXT: blt a1, a0, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_sge:
; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_slt:
; CHECK: # %bb.0:
; CHECK-NEXT: blt a0, a1, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}
define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_sle:
; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, half %c, half %d
ret half %2
}