forked from OSchip/llvm-project
parent
99bf133d58
commit
3968263ca8
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@ -70,6 +70,16 @@ class DFPBinOp<string OpcStr, SDNode OpNode> :
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!strconcat(OpcStr, " $dst, $a, $b"),
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[(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
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class FPUnaryOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops FPRegs:$dst, FPRegs:$src),
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!strconcat(OpcStr, " $dst, $src"),
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[(set FPRegs:$dst, (OpNode FPRegs:$src))]>;
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class DFPUnaryOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
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!strconcat(OpcStr, " $dst, $src"),
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[(set DFPRegs:$dst, (OpNode DFPRegs:$src))]>;
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class Addr1BinOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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!strconcat(OpcStr, " $dst, $a, $b"),
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@ -280,21 +290,10 @@ def FADDD : DFPBinOp<"faddd", fadd>;
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def FSUBS : FPBinOp<"fsubs", fsub>;
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def FSUBD : DFPBinOp<"fsubd", fsub>;
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def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"fnegs $dst, $src",
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[(set FPRegs:$dst, (fneg FPRegs:$src))]>;
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def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
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"fnegd $dst, $src",
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[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
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def FABSS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"fabss $dst, $src",
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[(set FPRegs:$dst, (fabs FPRegs:$src))]>;
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def FABSD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
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"fabsd $dst, $src",
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[(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
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def FNEGS : FPUnaryOp<"fnegs", fneg>;
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def FNEGD : DFPUnaryOp<"fnegd", fneg>;
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def FABSS : FPUnaryOp<"fabss", fabs>;
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def FABSD : DFPUnaryOp<"fabsd", fabs>;
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def FMULS : FPBinOp<"fmuls", fmul>;
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def FMULD : DFPBinOp<"fmuld", fmul>;
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