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[RISCV] Do not mandate scheduling for CSR instructions 

Scheduling information is of little value when they may disrupt the
pipeline.  This patch allows omitting the scheduling information for CSR
instructions while still setting `SchedMachineModel::CompleteModel`.  For
specific cases, any scheduling information added will be used by the
scheduler.

Differential revision: https://reviews.llvm.org/D85366
This commit is contained in:
Evandro Menezes 2020-08-05 16:51:05 -05:00
parent 161159888b
commit 394d020167
1 changed files with 4 additions and 2 deletions
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6
llvm/lib/Target/RISCV/RISCVInstrInfo.td
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@ -368,12 +368,14 @@ class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
: RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
opcodestr, "$rd, $rs1, $rs2">;
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
let hasNoSchedulingInfo = 1,
hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
class CSR_ir<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
let hasNoSchedulingInfo = 1,
hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
class CSR_ii<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
(ins csr_sysreg:$imm12, uimm5:$rs1),