forked from OSchip/llvm-project
[ARM][MVE] Restrict allowed types of gather/scatter offsets
The MVE gather instructions smaller than 32bits zext extend the values in the offset register, as opposed to sign extending them. We need to make sure that the code that we select from is suitably extended, which this patch attempts to fix by tightening up the offset checks. Differential Revision: https://reviews.llvm.org/D75361
This commit is contained in:
Anna Welker
parent
4962a0b26a
commit
394974111b
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@ -145,26 +145,35 @@ Value *MVEGatherScatterLowering::checkGEP(Value *&Offsets, Type *Ty, Value *Ptr,
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return nullptr;
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}
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Offsets = GEP->getOperand(1);
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// SExt offsets inside masked gathers are not permitted by the architecture;
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// we therefore can't fold them
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// Paranoid check whether the number of parallel lanes is the same
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assert(Ty->getVectorNumElements() ==
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Offsets->getType()->getVectorNumElements());
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// Only <N x i32> offsets can be integrated into an arm gather, any smaller
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// type would have to be sign extended by the gep - and arm gathers can only
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// zero extend. Additionally, the offsets do have to originate from a zext of
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// a vector with element types smaller or equal the type of the gather we're
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// looking at
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if (Offsets->getType()->getScalarSizeInBits() != 32)
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return nullptr;
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if (ZExtInst *ZextOffs = dyn_cast<ZExtInst>(Offsets))
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Offsets = ZextOffs->getOperand(0);
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Type *OffsType = VectorType::getInteger(cast<VectorType>(Ty));
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// If the offset we found does not have the type the intrinsic expects,
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// i.e., the same type as the gather (or scatter input) itself, we need to
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// convert it (only i types) or fall back to expanding the gather
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if (OffsType != Offsets->getType()) {
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if (OffsType->getScalarSizeInBits() >
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Offsets->getType()->getScalarSizeInBits()) {
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LLVM_DEBUG(dbgs() << "masked gathers/scatters: extending offsets\n");
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Offsets = Builder.CreateZExt(Offsets, OffsType, "");
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} else {
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else if (!(Offsets->getType()->getVectorNumElements() == 4 &&
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Offsets->getType()->getScalarSizeInBits() == 32))
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return nullptr;
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if (Ty != Offsets->getType()) {
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if ((Ty->getScalarSizeInBits() <
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Offsets->getType()->getScalarSizeInBits())) {
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LLVM_DEBUG(dbgs() << "masked gathers/scatters: no correct offset type."
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<< " Can't create intrinsic.\n");
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return nullptr;
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} else {
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Offsets = Builder.CreateZExt(
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Offsets, VectorType::getInteger(cast<VectorType>(Ty)));
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}
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}
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// If none of the checks failed, return the gep's base pointer
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LLVM_DEBUG(dbgs() << "masked gathers/scatters: found correct offsets\n");
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return GEPPtr;
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}
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@ -16,6 +16,137 @@ entry:
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ret <8 x i16> %gather.zext
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_unscaled_i8_i16_noext(i8* %base, <8 x i8>* %offptr) {
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; CHECK-LABEL: zext_unscaled_i8_i16_noext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vldrb.s32 q0, [r1]
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; CHECK-NEXT: vldrb.s32 q1, [r1, #4]
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vmov r2, s3
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; CHECK-NEXT: vmov r3, s1
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; CHECK-NEXT: vmov r5, s0
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov r1, s5
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; CHECK-NEXT: vmov r4, s7
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; CHECK-NEXT: ldrb.w r12, [r2]
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; CHECK-NEXT: vmov r2, s2
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; CHECK-NEXT: ldrb.w lr, [r3]
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; CHECK-NEXT: vmov r3, s6
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; CHECK-NEXT: ldrb r5, [r5]
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; CHECK-NEXT: ldrb r0, [r0]
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; CHECK-NEXT: vmov.16 q0[0], r5
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; CHECK-NEXT: ldrb r1, [r1]
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; CHECK-NEXT: vmov.16 q0[1], lr
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; CHECK-NEXT: ldrb r4, [r4]
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; CHECK-NEXT: ldrb r2, [r2]
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; CHECK-NEXT: ldrb r3, [r3]
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; CHECK-NEXT: vmov.16 q0[2], r2
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; CHECK-NEXT: vmov.16 q0[3], r12
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.16 q0[5], r1
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; CHECK-NEXT: vmov.16 q0[6], r3
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; CHECK-NEXT: vmov.16 q0[7], r4
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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entry:
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%offs = load <8 x i8>, <8 x i8>* %offptr, align 2
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%ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %offs
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%gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %ptrs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)
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%gather.zext = zext <8 x i8> %gather to <8 x i16>
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ret <8 x i16> %gather.zext
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}
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define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_sext(i16* %base, <8 x i8>* %offptr) {
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; CHECK-LABEL: scaled_v8i16_sext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vldrb.s32 q0, [r1]
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; CHECK-NEXT: vldrb.s32 q1, [r1, #4]
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; CHECK-NEXT: vshl.i32 q0, q0, #1
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; CHECK-NEXT: vshl.i32 q1, q1, #1
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vmov r2, s2
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; CHECK-NEXT: vmov r3, s3
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; CHECK-NEXT: vmov r5, s1
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov r1, s5
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; CHECK-NEXT: vmov r4, s7
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; CHECK-NEXT: ldrh.w r12, [r2]
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: ldrh.w lr, [r3]
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; CHECK-NEXT: vmov r3, s6
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; CHECK-NEXT: ldrh r5, [r5]
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; CHECK-NEXT: ldrh r0, [r0]
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; CHECK-NEXT: ldrh r1, [r1]
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; CHECK-NEXT: ldrh r4, [r4]
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; CHECK-NEXT: ldrh r2, [r2]
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; CHECK-NEXT: ldrh r3, [r3]
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; CHECK-NEXT: vmov.16 q0[0], r2
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; CHECK-NEXT: vmov.16 q0[1], r5
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; CHECK-NEXT: vmov.16 q0[2], r12
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; CHECK-NEXT: vmov.16 q0[3], lr
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.16 q0[5], r1
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; CHECK-NEXT: vmov.16 q0[6], r3
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; CHECK-NEXT: vmov.16 q0[7], r4
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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entry:
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%offs = load <8 x i8>, <8 x i8>* %offptr, align 2
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%offs.sext = sext <8 x i8> %offs to <8 x i16>
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%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %offs.sext
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%gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)
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ret <8 x i16> %gather
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}
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define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_zext(i16* %base, <8 x i8>* %offptr) {
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; CHECK-LABEL: scaled_v8i16_zext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vldrb.u32 q0, [r1]
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; CHECK-NEXT: vldrb.u32 q1, [r1, #4]
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; CHECK-NEXT: vshl.i32 q0, q0, #1
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; CHECK-NEXT: vshl.i32 q1, q1, #1
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vmov r2, s2
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; CHECK-NEXT: vmov r3, s3
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; CHECK-NEXT: vmov r5, s1
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov r1, s5
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; CHECK-NEXT: vmov r4, s7
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; CHECK-NEXT: ldrh.w r12, [r2]
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: ldrh.w lr, [r3]
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; CHECK-NEXT: vmov r3, s6
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; CHECK-NEXT: ldrh r5, [r5]
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; CHECK-NEXT: ldrh r0, [r0]
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; CHECK-NEXT: ldrh r1, [r1]
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; CHECK-NEXT: ldrh r4, [r4]
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; CHECK-NEXT: ldrh r2, [r2]
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; CHECK-NEXT: ldrh r3, [r3]
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; CHECK-NEXT: vmov.16 q0[0], r2
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; CHECK-NEXT: vmov.16 q0[1], r5
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; CHECK-NEXT: vmov.16 q0[2], r12
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; CHECK-NEXT: vmov.16 q0[3], lr
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.16 q0[5], r1
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; CHECK-NEXT: vmov.16 q0[6], r3
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; CHECK-NEXT: vmov.16 q0[7], r4
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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entry:
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%offs = load <8 x i8>, <8 x i8>* %offptr, align 2
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%offs.zext = zext <8 x i8> %offs to <8 x i16>
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%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %offs.zext
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%gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)
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ret <8 x i16> %gather
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}
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define arm_aapcs_vfpcc <8 x i16> @sext_unscaled_i8_i16(i8* %base, <8 x i16>* %offptr) {
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; CHECK-LABEL: sext_unscaled_i8_i16:
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; CHECK: @ %bb.0: @ %entry
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