diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp index 1806e015f61e..a281a0aa6bcc 100644 --- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -7,12 +7,16 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/SystemZMCTargetDesc.h" #include "SystemZ.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetRegistry.h" +#include +#include using namespace llvm; @@ -21,17 +25,19 @@ using namespace llvm; typedef MCDisassembler::DecodeStatus DecodeStatus; namespace { + class SystemZDisassembler : public MCDisassembler { public: SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) {} - ~SystemZDisassembler() override {} + ~SystemZDisassembler() override = default; DecodeStatus getInstruction(MCInst &instr, uint64_t &Size, ArrayRef Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const override; }; + } // end anonymous namespace static MCDisassembler *createSystemZDisassembler(const Target &T, diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp index 7082abad716d..092eb4011adc 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp @@ -11,20 +11,28 @@ // //===----------------------------------------------------------------------===// -#include "MCTargetDesc/SystemZMCTargetDesc.h" #include "MCTargetDesc/SystemZMCFixups.h" +#include "MCTargetDesc/SystemZMCTargetDesc.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include +#include using namespace llvm; #define DEBUG_TYPE "mccodeemitter" namespace { + class SystemZMCCodeEmitter : public MCCodeEmitter { const MCInstrInfo &MCII; MCContext &Ctx; @@ -34,7 +42,7 @@ public: : MCII(mcii), Ctx(ctx) { } - ~SystemZMCCodeEmitter() override {} + ~SystemZMCCodeEmitter() override = default; // OVerride MCCodeEmitter. void encodeInstruction(const MCInst &MI, raw_ostream &OS, @@ -137,13 +145,8 @@ private: void verifyInstructionPredicates(const MCInst &MI, uint64_t AvailableFeatures) const; }; -} // end anonymous namespace -MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, - const MCRegisterInfo &MRI, - MCContext &Ctx) { - return new SystemZMCCodeEmitter(MCII, Ctx); -} +} // end anonymous namespace void SystemZMCCodeEmitter:: encodeInstruction(const MCInst &MI, raw_ostream &OS, @@ -282,3 +285,9 @@ SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum, #define ENABLE_INSTR_PREDICATE_VERIFIER #include "SystemZGenMCCodeEmitter.inc" + +MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + MCContext &Ctx) { + return new SystemZMCCodeEmitter(MCII, Ctx); +} diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp index 43a96e84289c..3de570bf30cc 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp @@ -7,35 +7,38 @@ // //===----------------------------------------------------------------------===// -#include "MCTargetDesc/SystemZMCTargetDesc.h" #include "MCTargetDesc/SystemZMCFixups.h" +#include "MCTargetDesc/SystemZMCTargetDesc.h" #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCValue.h" +#include "llvm/Support/ELF.h" +#include "llvm/Support/ErrorHandling.h" +#include +#include using namespace llvm; namespace { + class SystemZObjectWriter : public MCELFObjectTargetWriter { public: SystemZObjectWriter(uint8_t OSABI); - - ~SystemZObjectWriter() override; + ~SystemZObjectWriter() override = default; protected: // Override MCELFObjectTargetWriter. unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override; }; + } // end anonymous namespace SystemZObjectWriter::SystemZObjectWriter(uint8_t OSABI) : MCELFObjectTargetWriter(/*Is64Bit=*/true, OSABI, ELF::EM_S390, /*HasRelocationAddend=*/ true) {} -SystemZObjectWriter::~SystemZObjectWriter() { -} - // Return the relocation type for an absolute value of MCFixupKind Kind. static unsigned getAbsoluteReloc(unsigned Kind) { switch (Kind) { diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp index 3b2077304ae9..d70f9e90cd3e 100644 --- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -13,15 +13,23 @@ // //===----------------------------------------------------------------------===// +#include "SystemZ.h" +#include "SystemZInstrInfo.h" #include "SystemZTargetMachine.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/IR/Function.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetSubtargetInfo.h" +#include +#include using namespace llvm; @@ -33,11 +41,11 @@ STATISTIC(EliminatedComparisons, "Number of eliminated comparisons"); STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions"); namespace { + // Represents the references to a particular register in one or more // instructions. struct Reference { - Reference() - : Def(false), Use(false) {} + Reference() = default; Reference &operator|=(const Reference &Other) { Def |= Other.Def; @@ -49,15 +57,16 @@ struct Reference { // True if the register is defined or used in some form, either directly or // via a sub- or super-register. - bool Def; - bool Use; + bool Def = false; + bool Use = false; }; class SystemZElimCompare : public MachineFunctionPass { public: static char ID; + SystemZElimCompare(const SystemZTargetMachine &tm) - : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {} + : MachineFunctionPass(ID) {} StringRef getPassName() const override { return "SystemZ Comparison Elimination"; @@ -65,6 +74,7 @@ public: bool processBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F) override; + MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( MachineFunctionProperties::Property::NoVRegs); @@ -84,16 +94,13 @@ private: bool fuseCompareOperations(MachineInstr &Compare, SmallVectorImpl &CCUsers); - const SystemZInstrInfo *TII; - const TargetRegisterInfo *TRI; + const SystemZInstrInfo *TII = nullptr; + const TargetRegisterInfo *TRI = nullptr; }; char SystemZElimCompare::ID = 0; -} // end anonymous namespace -FunctionPass *llvm::createSystemZElimComparePass(SystemZTargetMachine &TM) { - return new SystemZElimCompare(TM); -} +} // end anonymous namespace // Return true if CC is live out of MBB. static bool isCCLiveOut(MachineBasicBlock &MBB) { @@ -167,7 +174,7 @@ static unsigned getCompareSourceReg(MachineInstr &Compare) { reg = Compare.getOperand(0).getReg(); else if (isLoadAndTestAsCmp(Compare)) reg = Compare.getOperand(1).getReg(); - assert (reg); + assert(reg); return reg; } @@ -366,10 +373,8 @@ static bool isCompareZero(MachineInstr &Compare) { return true; default: - if (isLoadAndTestAsCmp(Compare)) return true; - return Compare.getNumExplicitOperands() == 2 && Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0; } @@ -571,3 +576,7 @@ bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) { return Changed; } + +FunctionPass *llvm::createSystemZElimComparePass(SystemZTargetMachine &TM) { + return new SystemZElimCompare(TM); +} diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 4c65899024e4..0e2ed5988650 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -11,12 +11,34 @@ // //===----------------------------------------------------------------------===// -#include "SystemZInstrInfo.h" +#include "MCTargetDesc/SystemZMCTargetDesc.h" +#include "SystemZ.h" #include "SystemZInstrBuilder.h" -#include "SystemZTargetMachine.h" -#include "llvm/CodeGen/LiveVariables.h" +#include "SystemZInstrInfo.h" +#include "SystemZSubtarget.h" +#include "llvm/CodeGen/LiveInterval.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Support/BranchProbability.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetSubtargetInfo.h" +#include +#include +#include using namespace llvm; @@ -255,7 +277,6 @@ void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB, .addImm(32 - Size).addImm(128 + 31).addImm(Rotate); } - MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, @@ -284,7 +305,6 @@ MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI, } } - // If MI is a simple load or store for a frame object, return the register // it loads or stores and set FrameIndex to the index of the frame object. // Return 0 otherwise. @@ -588,7 +608,6 @@ bool SystemZInstrInfo::optimizeCompareInstr( removeIPMBasedCompare(Compare, SrcReg, MRI, &RI); } - bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, ArrayRef Pred, unsigned TrueReg, unsigned FalseReg, @@ -892,15 +911,19 @@ static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) { } namespace { + struct LogicOp { - LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} + LogicOp() = default; LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} explicit operator bool() const { return RegSize; } - unsigned RegSize, ImmLSB, ImmSize; + unsigned RegSize = 0; + unsigned ImmLSB = 0; + unsigned ImmSize = 0; }; + } // end anonymous namespace static LogicOp interpretAndImmediate(unsigned Opcode) { @@ -1044,7 +1067,7 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl( MCRegUnitIterator CCUnit(SystemZ::CC, TRI); LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit); ++CCUnit; - assert (!CCUnit.isValid() && "CC only has one reg unit."); + assert(!CCUnit.isValid() && "CC only has one reg unit."); SlotIndex MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot(); if (!CCLiveRange.liveAt(MISlot)) { diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index d44ce719b7fa..b07f101d4cb9 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -16,16 +16,21 @@ #include "SystemZ.h" #include "SystemZRegisterInfo.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/TargetInstrInfo.h" +#include #define GET_INSTRINFO_HEADER #include "SystemZGenInstrInfo.inc" namespace llvm { -class SystemZTargetMachine; +class SystemZSubtarget; namespace SystemZII { + enum { // See comments in SystemZInstrFormats.td. SimpleBDXLoad = (1 << 0), @@ -43,12 +48,15 @@ enum { CCMaskLast = (1 << 19), IsLogical = (1 << 20) }; + static inline unsigned getAccessSize(unsigned int Flags) { return (Flags & AccessSizeMask) >> AccessSizeShift; } + static inline unsigned getCCValues(unsigned int Flags) { return (Flags & CCValuesMask) >> CCValuesShift; } + static inline unsigned getCompareZeroCCMask(unsigned int Flags) { return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift; } @@ -64,6 +72,7 @@ enum { // @INDNTPOFF MO_INDNTPOFF = (2 << 0) }; + // Classifies a branch. enum BranchType { // An instruction that branches on the current value of CC. @@ -93,6 +102,7 @@ enum BranchType { // the result is nonzero. BranchCTG }; + // Information about a branch instruction. struct Branch { // The type of the branch. @@ -111,6 +121,7 @@ struct Branch { const MachineOperand *target) : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {} }; + // Kinds of fused compares in compare-and-* instructions. Together with type // of the converted compare, this identifies the compare-and-* // instruction. @@ -127,9 +138,9 @@ enum FusedCompareType { // Trap CompareAndTrap }; + } // end namespace SystemZII -class SystemZSubtarget; class SystemZInstrInfo : public SystemZGenInstrInfo { const SystemZRegisterInfo RI; SystemZSubtarget &STI; @@ -305,6 +316,7 @@ public: areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA = nullptr) const override; }; + } // end namespace llvm -#endif +#endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp index c466faba9c8f..791f0334e0f1 100644 --- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp +++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp @@ -53,15 +53,21 @@ // //===----------------------------------------------------------------------===// +#include "SystemZ.h" +#include "SystemZInstrInfo.h" #include "SystemZTargetMachine.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/IR/Function.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/Support/ErrorHandling.h" +#include +#include using namespace llvm; @@ -70,72 +76,72 @@ using namespace llvm; STATISTIC(LongBranches, "Number of long branches."); namespace { + // Represents positional information about a basic block. struct MBBInfo { // The address that we currently assume the block has. - uint64_t Address; + uint64_t Address = 0; // The size of the block in bytes, excluding terminators. // This value never changes. - uint64_t Size; + uint64_t Size = 0; // The minimum alignment of the block, as a log2 value. // This value never changes. - unsigned Alignment; + unsigned Alignment = 0; // The number of terminators in this block. This value never changes. - unsigned NumTerminators; + unsigned NumTerminators = 0; - MBBInfo() - : Address(0), Size(0), Alignment(0), NumTerminators(0) {} + MBBInfo() = default; }; // Represents the state of a block terminator. struct TerminatorInfo { // If this terminator is a relaxable branch, this points to the branch // instruction, otherwise it is null. - MachineInstr *Branch; + MachineInstr *Branch = nullptr; // The address that we currently assume the terminator has. - uint64_t Address; + uint64_t Address = 0; // The current size of the terminator in bytes. - uint64_t Size; + uint64_t Size = 0; // If Branch is nonnull, this is the number of the target block, // otherwise it is unused. - unsigned TargetBlock; + unsigned TargetBlock = 0; // If Branch is nonnull, this is the length of the longest relaxed form, // otherwise it is zero. - unsigned ExtraRelaxSize; + unsigned ExtraRelaxSize = 0; - TerminatorInfo() : Branch(nullptr), Size(0), TargetBlock(0), - ExtraRelaxSize(0) {} + TerminatorInfo() = default; }; // Used to keep track of the current position while iterating over the blocks. struct BlockPosition { // The address that we assume this position has. - uint64_t Address; + uint64_t Address = 0; // The number of low bits in Address that are known to be the same // as the runtime address. unsigned KnownBits; - BlockPosition(unsigned InitialAlignment) - : Address(0), KnownBits(InitialAlignment) {} + BlockPosition(unsigned InitialAlignment) : KnownBits(InitialAlignment) {} }; class SystemZLongBranch : public MachineFunctionPass { public: static char ID; + SystemZLongBranch(const SystemZTargetMachine &tm) - : MachineFunctionPass(ID), TII(nullptr) {} + : MachineFunctionPass(ID) {} StringRef getPassName() const override { return "SystemZ Long Branch"; } bool runOnMachineFunction(MachineFunction &F) override; + MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( MachineFunctionProperties::Property::NoVRegs); @@ -155,7 +161,7 @@ private: void relaxBranch(TerminatorInfo &Terminator); void relaxBranches(); - const SystemZInstrInfo *TII; + const SystemZInstrInfo *TII = nullptr; MachineFunction *MF; SmallVector MBBs; SmallVector Terminators; @@ -165,11 +171,8 @@ char SystemZLongBranch::ID = 0; const uint64_t MaxBackwardRange = 0x10000; const uint64_t MaxForwardRange = 0xfffe; -} // end anonymous namespace -FunctionPass *llvm::createSystemZLongBranchPass(SystemZTargetMachine &TM) { - return new SystemZLongBranch(TM); -} +} // end anonymous namespace // Position describes the state immediately before Block. Update Block // accordingly and move Position to the end of the block's non-terminator @@ -463,3 +466,7 @@ bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) { relaxBranches(); return true; } + +FunctionPass *llvm::createSystemZLongBranchPass(SystemZTargetMachine &TM) { + return new SystemZLongBranch(TM); +} diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h index b919758b70e7..12357e0348a9 100644 --- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h +++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h @@ -1,4 +1,4 @@ -//==-- SystemZMachineScheduler.h - SystemZ Scheduler Interface -*- C++ -*---==// +//==- SystemZMachineScheduler.h - SystemZ Scheduler Interface ----*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -14,10 +14,10 @@ // usage of processor resources. //===----------------------------------------------------------------------===// -#include "SystemZInstrInfo.h" #include "SystemZHazardRecognizer.h" #include "llvm/CodeGen/MachineScheduler.h" -#include "llvm/Support/Debug.h" +#include "llvm/CodeGen/ScheduleDAG.h" +#include #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H @@ -28,29 +28,29 @@ namespace llvm { /// A MachineSchedStrategy implementation for SystemZ post RA scheduling. class SystemZPostRASchedStrategy : public MachineSchedStrategy { - ScheduleDAGMI *DAG; + ScheduleDAGMI *DAG; /// A candidate during instruction evaluation. struct Candidate { - SUnit *SU; + SUnit *SU = nullptr; /// The decoding cost. - int GroupingCost; + int GroupingCost = 0; /// The processor resources cost. - int ResourcesCost; + int ResourcesCost = 0; - Candidate() : SU(nullptr), GroupingCost(0), ResourcesCost(0) {} + Candidate() = default; Candidate(SUnit *SU_, SystemZHazardRecognizer &HazardRec); // Compare two candidates. bool operator<(const Candidate &other); // Check if this node is free of cost ("as good as any"). - bool inline noCost() { + bool noCost() const { return (GroupingCost <= 0 && !ResourcesCost); } - }; + }; // A sorter for the Available set that makes sure that SUs are considered // in the best order. @@ -83,7 +83,7 @@ class SystemZPostRASchedStrategy : public MachineSchedStrategy { // region. SystemZHazardRecognizer HazardRec; - public: +public: SystemZPostRASchedStrategy(const MachineSchedContext *C); /// PostRA scheduling does not track pressure. @@ -107,6 +107,6 @@ class SystemZPostRASchedStrategy : public MachineSchedStrategy { void releaseBottomNode(SUnit *SU) override {}; }; -} // namespace llvm +} // end namespace llvm -#endif /* LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H */ +#endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index 33fdb8f90825..ede5005fa491 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -7,14 +7,25 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/SystemZMCTargetDesc.h" +#include "SystemZ.h" +#include "SystemZMachineScheduler.h" #include "SystemZTargetMachine.h" #include "SystemZTargetTransformInfo.h" -#include "SystemZMachineScheduler.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/TargetPassConfig.h" -#include "llvm/Support/TargetRegistry.h" -#include "llvm/Transforms/Scalar.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Support/CodeGen.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Target/TargetLoweringObjectFile.h" +#include "llvm/Transforms/Scalar.h" +#include using namespace llvm; @@ -48,7 +59,7 @@ static bool UsesVectorABI(StringRef CPU, StringRef FS) { static std::string computeDataLayout(const Triple &TT, StringRef CPU, StringRef FS) { bool VectorABI = UsesVectorABI(CPU, FS); - std::string Ret = ""; + std::string Ret; // Big endian. Ret += "E"; @@ -96,14 +107,15 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), - TLOF(make_unique()), + TLOF(llvm::make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } -SystemZTargetMachine::~SystemZTargetMachine() {} +SystemZTargetMachine::~SystemZTargetMachine() = default; namespace { + /// SystemZ Code Generator Pass Configuration Options. class SystemZPassConfig : public TargetPassConfig { public: @@ -116,7 +128,8 @@ public: ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override { - return new ScheduleDAGMI(C, make_unique(C), + return new ScheduleDAGMI(C, + llvm::make_unique(C), /*RemoveKillFlags=*/true); } @@ -126,6 +139,7 @@ public: void addPreSched2() override; void addPreEmitPass() override; }; + } // end anonymous namespace void SystemZPassConfig::addIRPasses() { @@ -157,7 +171,6 @@ void SystemZPassConfig::addPreSched2() { } void SystemZPassConfig::addPreEmitPass() { - // Do instruction shortening before compare elimination because some // vector instructions will be shortened into opcodes that compare // elimination recognizes. diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h index 69cf9bc6e525..a10ca64fa632 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -1,4 +1,4 @@ -//==- SystemZTargetMachine.h - Define TargetMachine for SystemZ ---*- C++ -*-=// +//=- SystemZTargetMachine.h - Define TargetMachine for SystemZ ----*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -16,15 +16,18 @@ #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZTARGETMACHINE_H #include "SystemZSubtarget.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetMachine.h" +#include namespace llvm { -class TargetFrameLowering; - class SystemZTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; - SystemZSubtarget Subtarget; + SystemZSubtarget Subtarget; public: SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, @@ -34,20 +37,22 @@ public: ~SystemZTargetMachine() override; const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } + const SystemZSubtarget *getSubtargetImpl(const Function &) const override { return &Subtarget; } + // Override LLVMTargetMachine TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetIRAnalysis getTargetIRAnalysis() override; + TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } bool targetSchedulesPostRAScheduling() const override { return true; }; - }; } // end namespace llvm -#endif +#endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZTARGETMACHINE_H