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[X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions 

If the question mark is inside the parentheses it only applies to the single character proceeding it.

I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this.

llvm-svn: 320279
This commit is contained in:
Craig Topper 2017-12-10 01:24:08 +00:00
parent 8ee98d0b51
commit 391c6f9507
13 changed files with 496 additions and 504 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

103
llvm/lib/Target/X86/X86SchedBroadwell.td
View File

@ -403,18 +403,18 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKLBWirr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKLDQirr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKLWDirr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOV64toPQIrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVAPDrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVAPSrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVAPDrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVAPSrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVDDUPrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVDI2PDIrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVHLPSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVLHPSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVSDrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVSDrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVSHDUPrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVSLDUPrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVSSrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVUPDrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVUPSrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVSSrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVUPDrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "MOVUPSrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "ORPDrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "ORPSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "PACKSSDWrr")>;
@ -466,25 +466,25 @@ def: InstRW<[BWWriteResGroup3], (instregex "VANDPSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VBROADCASTSSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VINSERTPSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOV64toPQIrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPDYrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPDrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPSYrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPSrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPDYrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPDrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPSYrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPSrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVDDUPYrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVDDUPrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVDI2PDIrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVHLPSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVLHPSrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSDrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSDrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSHDUPYrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSHDUPrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSLDUPYrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSLDUPrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSSrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPDYrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPDrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPSYrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPSrr(_REV?)")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVSSrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPDYrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPDrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPSYrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPSrr(_REV)?")>;
def: InstRW<[BWWriteResGroup3], (instregex "VORPDYrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VORPDrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "VORPSYrr")>;
@ -591,8 +591,8 @@ def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADCX32rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADCX64rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADOX32rr")>;
@ -664,8 +664,8 @@ def: InstRW<[BWWriteResGroup6], (instregex "SAR8ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SARX32rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SARX64rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "SETAEr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SETBr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SETEr")>;
@ -881,13 +881,13 @@ def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
def: InstRW<[BWWriteResGroup8], (instregex "BLENDPDrri")>;
def: InstRW<[BWWriteResGroup8], (instregex "BLENDPSrri")>;
def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVD64from64rr")>;
def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr(_REV?)")>;
def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr(_REV)?")>;
def: InstRW<[BWWriteResGroup8], (instregex "MMX_PANDNirr")>;
def: InstRW<[BWWriteResGroup8], (instregex "MMX_PANDirr")>;
def: InstRW<[BWWriteResGroup8], (instregex "MMX_PORirr")>;
def: InstRW<[BWWriteResGroup8], (instregex "MMX_PXORirr")>;
def: InstRW<[BWWriteResGroup8], (instregex "MOVDQArr(_REV?)")>;
def: InstRW<[BWWriteResGroup8], (instregex "MOVDQUrr(_REV?)")>;
def: InstRW<[BWWriteResGroup8], (instregex "MOVDQArr(_REV)?")>;
def: InstRW<[BWWriteResGroup8], (instregex "MOVDQUrr(_REV)?")>;
def: InstRW<[BWWriteResGroup8], (instregex "MOVPQI2QIrr")>;
def: InstRW<[BWWriteResGroup8], (instregex "PANDNrr")>;
def: InstRW<[BWWriteResGroup8], (instregex "PANDrr")>;
@ -897,10 +897,10 @@ def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPDYrri")>;
def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPDrri")>;
def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPSYrri")>;
def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPSrri")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQAYrr(_REV?)")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQArr(_REV?)")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQUYrr(_REV?)")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQUrr(_REV?)")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQAYrr(_REV)?")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQArr(_REV)?")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQUYrr(_REV)?")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQUrr(_REV)?")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVPQI2QIrr")>;
def: InstRW<[BWWriteResGroup8], (instregex "VMOVZPQILo2PQIrr")>;
def: InstRW<[BWWriteResGroup8], (instregex "VPANDNYrr")>;
@ -920,33 +920,32 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "CBW")>;
def: InstRW<[BWWriteResGroup9], (instregex "CLC")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMC")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "CWDE")>;
def: InstRW<[BWWriteResGroup9], (instregex "DEC(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "DEC8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "INC(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "INC8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "LAHF")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri_alt")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri(_alt)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr8")>;
@ -958,10 +957,10 @@ def: InstRW<[BWWriteResGroup9], (instregex "NOOP")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOT(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOT8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "SAHF")>;
def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m")>;
def: InstRW<[BWWriteResGroup9], (instregex "SIDT64m")>;
@ -970,10 +969,10 @@ def: InstRW<[BWWriteResGroup9], (instregex "SMSW16m")>;
def: InstRW<[BWWriteResGroup9], (instregex "STC")>;
def: InstRW<[BWWriteResGroup9], (instregex "STRm")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
@ -981,10 +980,10 @@ def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8rr(_REV?)")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8rr(_REV)?")>;
def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
let Latency = 1;
@ -1252,8 +1251,7 @@ def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)r")>;
def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)r(mr)?")>;
def: InstRW<[BWWriteResGroup25], (instregex "PUSH64i8")>;
def: InstRW<[BWWriteResGroup25], (instregex "STOSB")>;
def: InstRW<[BWWriteResGroup25], (instregex "STOSL")>;
@ -1299,7 +1297,7 @@ def: InstRW<[BWWriteResGroup27], (instregex "COMISSrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CVTDQ2PSrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CVTPS2DQrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CVTTPS2DQrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "IMUL(32|64)rr(i8?)")>;
def: InstRW<[BWWriteResGroup27], (instregex "IMUL(32|64)rr(i8)?")>;
def: InstRW<[BWWriteResGroup27], (instregex "IMUL8r")>;
def: InstRW<[BWWriteResGroup27], (instregex "LZCNT(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup27], (instregex "MAX(C?)PDrr")>;
@ -1382,7 +1380,7 @@ def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup27_16], (instregex "IMUL16rr(i8?)")>;
def: InstRW<[BWWriteResGroup27_16], (instregex "IMUL16rr(i8)?")>;
def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
let Latency = 3;
@ -2383,8 +2381,7 @@ def: InstRW<[BWWriteResGroup66], (instregex "CMP8mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "OR(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "OR8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)r")>;
def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)r(mr)?")>;
def: InstRW<[BWWriteResGroup66], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "SUB8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "TEST(16|32|64)mr")>;
@ -2779,7 +2776,7 @@ def: InstRW<[BWWriteResGroup91], (instregex "CVTDQ2PSrm")>;
def: InstRW<[BWWriteResGroup91], (instregex "CVTPS2DQrm")>;
def: InstRW<[BWWriteResGroup91], (instregex "CVTTPS2DQrm")>;
def: InstRW<[BWWriteResGroup91], (instregex "IMUL64m")>;
def: InstRW<[BWWriteResGroup91], (instregex "IMUL(32|64)rm(i8?)")>;
def: InstRW<[BWWriteResGroup91], (instregex "IMUL(32|64)rm(i8)?")>;
def: InstRW<[BWWriteResGroup91], (instregex "IMUL8m")>;
def: InstRW<[BWWriteResGroup91], (instregex "LZCNT(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup91], (instregex "MAX(C?)PDrm")>;
@ -2842,7 +2839,7 @@ def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup91_16], (instregex "IMUL16rm(i8?)")>;
def: InstRW<[BWWriteResGroup91_16], (instregex "IMUL16rm(i8)?")>;
def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
let Latency = 8;
@ -3826,7 +3823,7 @@ def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
let NumMicroOps = 19;
let ResourceCycles = [3,1,15];
}
def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64?)")>;
def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let Latency = 24;
@ -3954,7 +3951,7 @@ def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPor
let NumMicroOps = 28;
let ResourceCycles = [1,6,1,1,19];
}
def: InstRW<[BWWriteResGroup186], (instregex "XSAVE(OPT?)")>;
def: InstRW<[BWWriteResGroup186], (instregex "XSAVE(OPT)?")>;
def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
let Latency = 31;

92
llvm/lib/Target/X86/X86SchedHaswell.td
View File

@ -977,12 +977,12 @@ def: InstRW<[HWWriteResGroup4], (instregex "MOVDDUPrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVDI2PDIrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVHLPSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVLHPSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVSDrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVSDrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVSHDUPrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVSLDUPrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVSSrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVUPDrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVUPSrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVSSrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVUPDrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "MOVUPSrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "ORPDrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "ORPSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "PACKSSDWrr")>;
@ -1034,25 +1034,25 @@ def: InstRW<[HWWriteResGroup4], (instregex "VANDPSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VBROADCASTSSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VINSERTPSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDYrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSYrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDYrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSYrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPYrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVDI2PDIrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVHLPSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVLHPSrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSDrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSDrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPYrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPYrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSSrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDYrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSYrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSrr(_REV?)")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVSSrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDYrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSYrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSrr(_REV)?")>;
def: InstRW<[HWWriteResGroup4], (instregex "VORPDYrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VORPDrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "VORPSYrr")>;
@ -1425,13 +1425,13 @@ def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
def: InstRW<[HWWriteResGroup9], (instregex "BLENDPDrri")>;
def: InstRW<[HWWriteResGroup9], (instregex "BLENDPSrri")>;
def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;
def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr(_REV?)")>;
def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr(_REV)?")>;
def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDNirr")>;
def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDirr")>;
def: InstRW<[HWWriteResGroup9], (instregex "MMX_PORirr")>;
def: InstRW<[HWWriteResGroup9], (instregex "MMX_PXORirr")>;
def: InstRW<[HWWriteResGroup9], (instregex "MOVDQArr(_REV?)")>;
def: InstRW<[HWWriteResGroup9], (instregex "MOVDQUrr(_REV?)")>;
def: InstRW<[HWWriteResGroup9], (instregex "MOVDQArr(_REV)?")>;
def: InstRW<[HWWriteResGroup9], (instregex "MOVDQUrr(_REV)?")>;
def: InstRW<[HWWriteResGroup9], (instregex "MOVPQI2QIrr")>;
def: InstRW<[HWWriteResGroup9], (instregex "PANDNrr")>;
def: InstRW<[HWWriteResGroup9], (instregex "PANDrr")>;
@ -1441,10 +1441,10 @@ def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDYrri")>;
def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDrri")>;
def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSYrri")>;
def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSrri")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQAYrr(_REV?)")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQArr(_REV?)")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUYrr(_REV?)")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUrr(_REV?)")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQAYrr(_REV)?")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQArr(_REV)?")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUYrr(_REV)?")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUrr(_REV)?")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVPQI2QIrr")>;
def: InstRW<[HWWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;
def: InstRW<[HWWriteResGroup9], (instregex "VPANDNYrr")>;
@ -1464,32 +1464,32 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "CWDE")>;
def: InstRW<[HWWriteResGroup10], (instregex "DEC(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "DEC8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri(_alt?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri(_alt)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
@ -1501,10 +1501,10 @@ def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>;
def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>;
def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>;
@ -1513,10 +1513,10 @@ def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
@ -1594,7 +1594,7 @@ def: InstRW<[HWWriteResGroup12], (instregex "FCOM64m")>;
def: InstRW<[HWWriteResGroup12], (instregex "FCOMP32m")>;
def: InstRW<[HWWriteResGroup12], (instregex "FCOMP64m")>;
def: InstRW<[HWWriteResGroup12], (instregex "IMUL(16|32|64)m")>;
def: InstRW<[HWWriteResGroup12], (instregex "IMUL(16|32|64)rm(i8?)")>;
def: InstRW<[HWWriteResGroup12], (instregex "IMUL(16|32|64)rm(i8)?")>;
def: InstRW<[HWWriteResGroup12], (instregex "IMUL8m")>;
def: InstRW<[HWWriteResGroup12], (instregex "LZCNT(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup12], (instregex "MAX(C?)SDrm")>;
@ -2084,7 +2084,7 @@ def: InstRW<[HWWriteResGroup18], (instregex "CMP8mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "OR(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "OR8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr?)")>;
def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr)?")>;
def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)mr")>;
@ -2164,7 +2164,7 @@ def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)r(mr?)")>;
def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)r(mr)?")>;
def: InstRW<[HWWriteResGroup24], (instregex "PUSH64i8")>;
def: InstRW<[HWWriteResGroup24], (instregex "STOSB")>;
def: InstRW<[HWWriteResGroup24], (instregex "STOSL")>;
@ -2355,10 +2355,10 @@ def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri8")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup35], (instregex "CMOVAE(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "CMOVB(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "CMOVE(16|32|64)rr")>;
@ -2376,10 +2376,10 @@ def: InstRW<[HWWriteResGroup35], (instregex "CMOVS(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "CWD")>;
def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri8")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr(_REV?)")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8rr(_REV?)")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8rr(_REV)?")>;
def: InstRW<[HWWriteResGroup35], (instregex "SETAr")>;
def: InstRW<[HWWriteResGroup35], (instregex "SETBEr")>;
@ -2597,7 +2597,7 @@ def: InstRW<[HWWriteResGroup50], (instregex "COMISSrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "CVTDQ2PSrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "CVTPS2DQrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "CVTTPS2DQrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "IMUL64rr(i8?)")>;
def: InstRW<[HWWriteResGroup50], (instregex "IMUL64rr(i8)?")>;
def: InstRW<[HWWriteResGroup50], (instregex "IMUL8r")>;
def: InstRW<[HWWriteResGroup50], (instregex "LZCNT(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup50], (instregex "MAX(C?)PDrr")>;
@ -2679,13 +2679,13 @@ def HWWriteResGroup50_16 : SchedWriteRes<[HWPort1, HWPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
}
def: InstRW<[HWWriteResGroup50_16], (instregex "IMUL16rr(i8?)")>;
def: InstRW<[HWWriteResGroup50_16], (instregex "IMUL16rr(i8)?")>;
def HWWriteResGroup50_32 : SchedWriteRes<[HWPort1, HWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
}
def: InstRW<[HWWriteResGroup50_32], (instregex "IMUL32rr(i8?)")>;
def: InstRW<[HWWriteResGroup50_32], (instregex "IMUL32rr(i8)?")>;
def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
let Latency = 3;
@ -4233,7 +4233,7 @@ def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
let NumMicroOps = 19;
let ResourceCycles = [3,1,15];
}
def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64?)")>;
def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
def HWWriteResGroup152 : SchedWriteRes<[HWPort0,HWPort5,HWPort015,HWPort0156]> {
let Latency = 19;
@ -4358,7 +4358,7 @@ def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPor
let NumMicroOps = 28;
let ResourceCycles = [1,6,1,1,19];
}
def: InstRW<[HWWriteResGroup165], (instregex "XSAVE(OPT?)")>;
def: InstRW<[HWWriteResGroup165], (instregex "XSAVE(OPT)?")>;
def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
let Latency = 34;

104
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -380,11 +380,11 @@ def: InstRW<[SKLWriteResGroup3], (instregex "MOVDDUPrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVDI2PDIrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVHLPSrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVLHPSrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVSDrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVSDrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVSHDUPrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVSLDUPrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPDrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPSrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPDrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPSrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "PACKSSDWrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "PACKSSWBrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "PACKUSDWrr")>;
@ -433,15 +433,15 @@ def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDDUPrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDI2PDIrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVHLPSrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVLHPSrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSDrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSDrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSHDUPYrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSHDUPrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSLDUPYrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSLDUPrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDYrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSYrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDYrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSYrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSDWYrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSDWrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSWBYrr")>;
@ -676,7 +676,7 @@ def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
}
def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP")>;
def: InstRW<[SKLWriteResGroup6], (instregex "FNOP")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVQ64rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVQ64rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSBrr64")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSDrr64")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSWrr64")>;
@ -702,8 +702,8 @@ def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADCX32rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADCX64rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADOX32rr")>;
@ -776,8 +776,8 @@ def: InstRW<[SKLWriteResGroup7], (instregex "SAR8ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SARX32rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SARX64rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SETAEr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SETBr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SETEr")>;
@ -835,12 +835,12 @@ def: InstRW<[SKLWriteResGroup9], (instregex "ANDPSrr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "BLENDPDrri")>;
def: InstRW<[SKLWriteResGroup9], (instregex "BLENDPSrri")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPDrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPSrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQArr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQUrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPDrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPSrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQArr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQUrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVPQI2QIrr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVSSrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "MOVSSrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "ORPDrr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "ORPSrr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "PADDBrr")>;
@ -867,16 +867,16 @@ def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPDYrri")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPDrri")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPSYrri")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPSrri")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDYrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSYrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQAYrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQArr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUYrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDYrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSYrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQAYrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQArr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUYrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVPQI2QIrr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVSSrr(_REV?)")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVSSrr(_REV)?")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VORPDYrr")>;
def: InstRW<[SKLWriteResGroup9], (instregex "VORPDrr")>;
@ -921,32 +921,32 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CBW")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CLC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CWDE")>;
def: InstRW<[SKLWriteResGroup10], (instregex "DEC(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "DEC8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri(_alt?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri(_alt)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
@ -958,10 +958,10 @@ def: InstRW<[SKLWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOT8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SAHF")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SIDT64m")>;
@ -970,10 +970,10 @@ def: InstRW<[SKLWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[SKLWriteResGroup10], (instregex "STC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "STRm")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
@ -981,10 +981,10 @@ def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8rr(_REV?)")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8rr(_REV)?")>;
def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
let Latency = 1;
@ -1282,8 +1282,7 @@ def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)r(mr)?")>;
def: InstRW<[SKLWriteResGroup28], (instregex "PUSH64i8")>;
def: InstRW<[SKLWriteResGroup28], (instregex "STOSB")>;
def: InstRW<[SKLWriteResGroup28], (instregex "STOSL")>;
@ -1297,7 +1296,7 @@ def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
}
def: InstRW<[SKLWriteResGroup29], (instregex "BSF(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup29], (instregex "BSR(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup29], (instregex "IMUL64rr(i8?)")>;
def: InstRW<[SKLWriteResGroup29], (instregex "IMUL64rr(i8)?")>;
def: InstRW<[SKLWriteResGroup29], (instregex "IMUL8r")>;
def: InstRW<[SKLWriteResGroup29], (instregex "LZCNT(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup29], (instregex "MUL8r")>;
@ -1315,13 +1314,13 @@ def SKLWriteResGroup29_16 : SchedWriteRes<[SKLPort1, SKLPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup29_16], (instregex "IMUL16rr(i8?)")>;
def: InstRW<[SKLWriteResGroup29_16], (instregex "IMUL16rr(i8)?")>;
def SKLWriteResGroup29_32 : SchedWriteRes<[SKLPort1]> {
let Latency = 3;
let NumMicroOps = 1;
}
def: InstRW<[SKLWriteResGroup29_32], (instregex "IMUL32rr(i8?)")>;
def: InstRW<[SKLWriteResGroup29_32], (instregex "IMUL32rr(i8)?")>;
def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
let Latency = 3;
@ -2230,8 +2229,7 @@ def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "OR(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "OR8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)r(mr)?")>;
def: InstRW<[SKLWriteResGroup76], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "SUB8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "TEST(16|32|64)mr")>;
@ -2776,7 +2774,7 @@ def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
def: InstRW<[SKLWriteResGroup107], (instregex "BSF(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "BSR(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "IMUL64m")>;
def: InstRW<[SKLWriteResGroup107], (instregex "IMUL(32|64)rm(i8?)")>;
def: InstRW<[SKLWriteResGroup107], (instregex "IMUL(32|64)rm(i8)?")>;
def: InstRW<[SKLWriteResGroup107], (instregex "IMUL8m")>;
def: InstRW<[SKLWriteResGroup107], (instregex "LZCNT(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "MUL(16|32|64)m")>;
@ -2793,7 +2791,7 @@ def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup107_16], (instregex "IMUL16rm(i8?)")>;
def: InstRW<[SKLWriteResGroup107_16], (instregex "IMUL16rm(i8)?")>;
def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
let Latency = 3;
@ -4119,7 +4117,7 @@ def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156
let NumMicroOps = 31;
let ResourceCycles = [1,8,1,21];
}
def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64?)")>;
def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
let Latency = 40;
@ -4147,7 +4145,7 @@ def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,
let NumMicroOps = 40;
let ResourceCycles = [1,11,1,1,26];
}
def: InstRW<[SKLWriteResGroup215], (instregex "XSAVE")>;
def: InstRW<[SKLWriteResGroup215], (instregex "^XSAVE$", "XSAVEC", "XSAVES")>;
def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 46;

171
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -424,11 +424,11 @@ def: InstRW<[SKXWriteResGroup3], (instregex "MOVDDUPrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVDI2PDIrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVHLPSrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVLHPSrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVSDrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVSDrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVSHDUPrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVSLDUPrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVUPDrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVUPSrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVUPDrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MOVUPSrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "PACKSSDWrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "PACKSSWBrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "PACKUSDWrr")>;
@ -487,7 +487,7 @@ def: InstRW<[SKXWriteResGroup3], (instregex "VMOVHLPSrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVLHPSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVLHPSrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSDZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSDrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSDrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSHDUPYrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSHDUPZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSHDUPZ256rr(b?)(k?)(z?)")>;
@ -498,11 +498,11 @@ def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSLDUPZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSLDUPZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSLDUPZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSLDUPrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSSZrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPDYrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPDrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPSYrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPSrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVSSZrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPDYrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPDrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPSYrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VMOVUPSrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPACKSSDWYrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPACKSSDWZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPACKSSDWZ256rr(b?)(k?)(z?)")>;
@ -979,7 +979,7 @@ def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
}
def: InstRW<[SKXWriteResGroup6], (instregex "FINCSTP")>;
def: InstRW<[SKXWriteResGroup6], (instregex "FNOP")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_MOVQ64rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_MOVQ64rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSBrr64")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSDrr64")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSWrr64")>;
@ -1005,8 +1005,8 @@ def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADCX32rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADCX64rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADOX32rr")>;
@ -1079,8 +1079,8 @@ def: InstRW<[SKXWriteResGroup7], (instregex "SAR8ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SARX32rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SARX64rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SETAEr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SETBr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SETEr")>;
@ -1138,12 +1138,12 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDPSrr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "BLENDPDrri")>;
def: InstRW<[SKXWriteResGroup9], (instregex "BLENDPSrri")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPDrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPSrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVDQArr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVDQUrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPDrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPSrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVDQArr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVDQUrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVPQI2QIrr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVSSrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "MOVSSrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "ORPDrr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "ORPSrr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "PADDBrr")>;
@ -1188,47 +1188,47 @@ def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDPDYrri")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDPDrri")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDPSYrri")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDPSrri")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDYrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDZ128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDZ256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDZrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPSYrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDYrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDZ128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDZ256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDZrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPDrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPSYrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPSrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA32Z128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA32Z256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA32Zrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA64Z128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVAPSrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA32Z128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA32Z256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA32Zrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA64Z128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA64Z256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA64Zrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQAYrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQArr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU16Z128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU16Z256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU16Zrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU32Z128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU32Z256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU32Zrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU64Z128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU64Z256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU64Zrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU8Z128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU8Z256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU8Zrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQUYrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQUrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQA64Zrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQAYrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQArr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU16Z128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU16Z256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU16Zrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU32Z128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU32Z256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU32Zrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU64Z128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU64Z256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU64Zrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU8Z128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU8Z256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQU8Zrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQUYrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVDQUrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVPQI(2Q|Lo2PQ)IZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVPQI2QIrr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVSSrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPDZ128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPDZ256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPDZrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPSZ128rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPSZ256rr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPSZrr(b?)(k?)(z?)(_REV?)")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVSSrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPDZ128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPDZ256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPDZrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPSZ128rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPSZ256rr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVUPSZrr(b?)(k?)(z?)(_REV)?")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VORPDYrr")>;
def: InstRW<[SKXWriteResGroup9], (instregex "VORPDZ128rr(b?)(k?)(z?)")>;
@ -1350,33 +1350,32 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CBW")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CLC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CWDE")>;
def: InstRW<[SKXWriteResGroup10], (instregex "DEC(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "DEC8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri_alt")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri(_alt)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
@ -1388,10 +1387,10 @@ def: InstRW<[SKXWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOT8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SAHF")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SGDT64m")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SIDT64m")>;
@ -1400,10 +1399,10 @@ def: InstRW<[SKXWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[SKXWriteResGroup10], (instregex "STC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "STRm")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>;
@ -1411,10 +1410,10 @@ def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8rr(_REV?)")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8rr(_REV)?")>;
def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
let Latency = 1;
@ -1797,8 +1796,7 @@ def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)r(mr)?")>;
def: InstRW<[SKXWriteResGroup28], (instregex "PUSH64i8")>;
def: InstRW<[SKXWriteResGroup28], (instregex "STOSB")>;
def: InstRW<[SKXWriteResGroup28], (instregex "STOSL")>;
@ -1841,7 +1839,7 @@ def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
}
def: InstRW<[SKXWriteResGroup31], (instregex "BSF(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup31], (instregex "BSR(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup31], (instregex "IMUL64rr(i8?)")>;
def: InstRW<[SKXWriteResGroup31], (instregex "IMUL64rr(i8)?")>;
def: InstRW<[SKXWriteResGroup31], (instregex "IMUL8r")>;
def: InstRW<[SKXWriteResGroup31], (instregex "LZCNT(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup31], (instregex "MUL8r")>;
@ -1859,13 +1857,13 @@ def SKXWriteResGroup31_16 : SchedWriteRes<[SKXPort1, SKXPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup31_16], (instregex "IMUL16rr(i8?)")>;
def: InstRW<[SKXWriteResGroup31_16], (instregex "IMUL16rr(i8)?")>;
def SKXWriteResGroup31_32 : SchedWriteRes<[SKXPort1]> {
let Latency = 3;
let NumMicroOps = 1;
}
def: InstRW<[SKXWriteResGroup31_32], (instregex "IMUL32rr(i8?)")>;
def: InstRW<[SKXWriteResGroup31_32], (instregex "IMUL32rr(i8)?")>;
def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
let Latency = 3;
@ -1918,8 +1916,8 @@ def: InstRW<[SKXWriteResGroup32], (instregex "VCMPPDZrri(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VCMPPSZ128rri(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VCMPPSZ256rri(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VCMPPSZrri(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VCMPSDZrr(_Int?)(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VCMPSSZrr(_Int?)(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VCMPSDZrr(_Int)?(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VCMPSSZrr(_Int)?(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VDBPSADBWZ128rri(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VDBPSADBWZ256rri(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup32], (instregex "VDBPSADBWZrri(b?)(k?)(z?)")>;
@ -2196,7 +2194,7 @@ def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRDZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRDrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRQZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRQrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWZrr(_REV?)")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWZrr(_REV)?")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWri")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWrr_REV")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPTESTYrr")>;
@ -2446,9 +2444,9 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSDZrr(_Int?)(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSDZrr(_Int)?(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSSZrr(_Int?)(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSSZrr(_Int)?(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSUBPDYrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSUBPDrr")>;
@ -2520,9 +2518,9 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132PSZ128r(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132PSZ256r(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132PSZr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132PSr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132SDZr(_Int?)(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132SDZr(_Int)?(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132SDr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132SSZr(_Int?)(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132SSZr(_Int)?(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD132SSr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD213PDYr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VFMADD213PDZ128r(b?)(k?)(z?)")>;
@ -3546,8 +3544,7 @@ def: InstRW<[SKXWriteResGroup81], (instregex "CMP8mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "OR(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "OR8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)r(mr)?")>;
def: InstRW<[SKXWriteResGroup81], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "SUB8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "TEST(16|32|64)mr")>;
@ -4362,7 +4359,7 @@ def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
def: InstRW<[SKXWriteResGroup118], (instregex "BSF(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup118], (instregex "BSR(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup118], (instregex "IMUL64m")>;
def: InstRW<[SKXWriteResGroup118], (instregex "IMUL(32|64)rm(i8?)")>;
def: InstRW<[SKXWriteResGroup118], (instregex "IMUL(32|64)rm(i8)?")>;
def: InstRW<[SKXWriteResGroup118], (instregex "IMUL8m")>;
def: InstRW<[SKXWriteResGroup118], (instregex "LZCNT(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup118], (instregex "MUL(16|32|64)m")>;
@ -4379,7 +4376,7 @@ def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]>
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup118_16_1], (instregex "IMUL16rm(i8?)")>;
def: InstRW<[SKXWriteResGroup118_16_1], (instregex "IMUL16rm(i8)?")>;
def SKXWriteResGroup118_16_2 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> {
let Latency = 8;
@ -6830,7 +6827,7 @@ def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156
let NumMicroOps = 31;
let ResourceCycles = [1,8,1,21];
}
def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64?)")>;
def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
def SKXWriteResGroup251 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 38;

16
llvm/test/CodeGen/X86/avx-schedule.ll
View File

@ -2077,14 +2077,14 @@ define <2 x double> @test_maskmovpd(i8* %a0, <2 x i64> %a1, <2 x double> %a2) {
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKYLAKE-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovapd %xmm2, %xmm0 # sched: [1:1.00]
; SKYLAKE-NEXT: vmovapd %xmm2, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovpd:
; SKX: # %bb.0:
; SKX-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKX-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovapd %xmm2, %xmm0 # sched: [1:1.00]
; SKX-NEXT: vmovapd %xmm2, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_maskmovpd:
@ -2140,14 +2140,14 @@ define <4 x double> @test_maskmovpd_ymm(i8* %a0, <4 x i64> %a1, <4 x double> %a2
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKYLAKE-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovapd %ymm2, %ymm0 # sched: [1:1.00]
; SKYLAKE-NEXT: vmovapd %ymm2, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovpd_ymm:
; SKX: # %bb.0:
; SKX-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKX-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovapd %ymm2, %ymm0 # sched: [1:1.00]
; SKX-NEXT: vmovapd %ymm2, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_maskmovpd_ymm:
@ -2203,14 +2203,14 @@ define <4 x float> @test_maskmovps(i8* %a0, <4 x i32> %a1, <4 x float> %a2) {
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKYLAKE-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:1.00]
; SKYLAKE-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovps:
; SKX: # %bb.0:
; SKX-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKX-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:1.00]
; SKX-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_maskmovps:
@ -2266,14 +2266,14 @@ define <8 x float> @test_maskmovps_ymm(i8* %a0, <8 x i32> %a1, <8 x float> %a2)
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKYLAKE-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovaps %ymm2, %ymm0 # sched: [1:1.00]
; SKYLAKE-NEXT: vmovaps %ymm2, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovps_ymm:
; SKX: # %bb.0:
; SKX-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKX-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovaps %ymm2, %ymm0 # sched: [1:1.00]
; SKX-NEXT: vmovaps %ymm2, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_maskmovps_ymm:

32
llvm/test/CodeGen/X86/avx2-schedule.ll
View File

@ -3391,28 +3391,28 @@ define <4 x i32> @test_pmaskmovd(i8* %a0, <4 x i32> %a1, <4 x i32> %a2) {
; HASWELL: # %bb.0:
; HASWELL-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [8:2.00]
; HASWELL-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [5:1.00]
; HASWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; HASWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_pmaskmovd:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [7:2.00]
; BROADWELL-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [5:1.00]
; BROADWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; BROADWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_pmaskmovd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKYLAKE-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovd:
; SKX: # %bb.0:
; SKX-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKX-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; SKX-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; ZNVER1-LABEL: test_pmaskmovd:
@ -3440,28 +3440,28 @@ define <8 x i32> @test_pmaskmovd_ymm(i8* %a0, <8 x i32> %a1, <8 x i32> %a2) {
; HASWELL: # %bb.0:
; HASWELL-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [9:2.00]
; HASWELL-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [5:1.00]
; HASWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; HASWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_pmaskmovd_ymm:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [8:2.00]
; BROADWELL-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [5:1.00]
; BROADWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; BROADWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_pmaskmovd_ymm:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKYLAKE-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovd_ymm:
; SKX: # %bb.0:
; SKX-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKX-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; SKX-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; ZNVER1-LABEL: test_pmaskmovd_ymm:
@ -3489,28 +3489,28 @@ define <2 x i64> @test_pmaskmovq(i8* %a0, <2 x i64> %a1, <2 x i64> %a2) {
; HASWELL: # %bb.0:
; HASWELL-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [8:2.00]
; HASWELL-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [5:1.00]
; HASWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; HASWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_pmaskmovq:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [7:2.00]
; BROADWELL-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [5:1.00]
; BROADWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; BROADWELL-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_pmaskmovq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKYLAKE-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovq:
; SKX: # %bb.0:
; SKX-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
; SKX-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
; SKX-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; ZNVER1-LABEL: test_pmaskmovq:
@ -3538,28 +3538,28 @@ define <4 x i64> @test_pmaskmovq_ymm(i8* %a0, <4 x i64> %a1, <4 x i64> %a2) {
; HASWELL: # %bb.0:
; HASWELL-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [9:2.00]
; HASWELL-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [5:1.00]
; HASWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; HASWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_pmaskmovq_ymm:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [8:2.00]
; BROADWELL-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [5:1.00]
; BROADWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; BROADWELL-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_pmaskmovq_ymm:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKYLAKE-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovq_ymm:
; SKX: # %bb.0:
; SKX-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
; SKX-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKX-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
; SKX-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; ZNVER1-LABEL: test_pmaskmovq_ymm:

14
llvm/test/CodeGen/X86/avx512-schedule.ll
View File

@ -994,7 +994,7 @@ define <8 x double> @test_mask_broadcast_vaddpd(<8 x double> %dst, <8 x double>
; SKX-NEXT: vpxor %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
; SKX-NEXT: vpcmpneqq %zmm0, %zmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vaddpd (%rdi){1to8}, %zmm1, %zmm1 {%k1} # sched: [11:0.50]
; SKX-NEXT: vmovapd %zmm1, %zmm0 # sched: [1:0.25]
; SKX-NEXT: vmovapd %zmm1, %zmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
%mask = icmp ne <8 x i64> %mask1, zeroinitializer
%tmp = load double, double* %j
@ -4558,9 +4558,9 @@ define <64 x i16> @test21(<64 x i16> %x , <64 x i1> %mask) nounwind readnone {
; SKX: # %bb.0:
; SKX-NEXT: vpsllw $7, %zmm2, %zmm2 # sched: [1:0.50]
; SKX-NEXT: vpmovb2m %zmm2, %k1 # sched: [1:1.00]
; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.25]
; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.33]
; SKX-NEXT: kshiftrq $32, %k1, %k1 # sched: [3:1.00]
; SKX-NEXT: vmovdqu16 %zmm1, %zmm1 {%k1} {z} # sched: [1:0.25]
; SKX-NEXT: vmovdqu16 %zmm1, %zmm1 {%k1} {z} # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
%ret = select <64 x i1> %mask, <64 x i16> %x, <64 x i16> zeroinitializer
ret <64 x i16> %ret
@ -7447,7 +7447,7 @@ define <32 x i16> @vmov_test21(<32 x i16> %x , <32 x i1> %mask) nounwind readnon
; SKX: # %bb.0:
; SKX-NEXT: vpsllw $7, %ymm1, %ymm1 # sched: [1:0.50]
; SKX-NEXT: vpmovb2m %ymm1, %k1 # sched: [1:1.00]
; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.25]
; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
%ret = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> zeroinitializer
ret <32 x i16> %ret
@ -7680,7 +7680,7 @@ define <32 x i16> @test_build_vec_v32i1(<32 x i16> %x) {
; SKX-NEXT: movl $1497715861, %eax # imm = 0x59455495
; SKX-NEXT: # sched: [1:0.25]
; SKX-NEXT: kmovd %eax, %k1 # sched: [1:1.00]
; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.25]
; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
%ret = select <32 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false>, <32 x i16> %x, <32 x i16> zeroinitializer
ret <32 x i16> %ret
@ -8454,7 +8454,7 @@ define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %m
; SKX-NEXT: vpxor %xmm3, %xmm3, %xmm3 # sched: [1:0.33]
; SKX-NEXT: vpcmpneqd %ymm3, %ymm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vbroadcastsd %xmm0, %zmm1 {%k1} # sched: [3:1.00]
; SKX-NEXT: vmovapd %zmm1, %zmm0 # sched: [1:0.25]
; SKX-NEXT: vmovapd %zmm1, %zmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
%mask = icmp ne <8 x i32> %mask1, zeroinitializer
%b = insertelement <8 x double> undef, double %a, i32 0
@ -8588,7 +8588,7 @@ define <16 x i32> @test_vbroadcast() {
; SKX-NEXT: vcmpunordps %zmm0, %zmm0, %k0 # sched: [3:1.00]
; SKX-NEXT: vpmovm2d %k0, %zmm0 # sched: [1:0.25]
; SKX-NEXT: knotw %k0, %k1 # sched: [1:1.00]
; SKX-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.25]
; SKX-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
entry:
%0 = sext <16 x i1> zeroinitializer to <16 x i32>

444
llvm/test/CodeGen/X86/avx512-shuffle-schedule.ll
View File

File diff suppressed because it is too large Load Diff

4
llvm/test/CodeGen/X86/mul-constant-i64.ll
View File

@ -1792,7 +1792,7 @@ define i64 @test_mul_spec(i64 %x) nounwind {
; X64-HSW-NEXT: addq $42, %rcx # sched: [1:0.25]
; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50]
; X64-HSW-NEXT: addq $2, %rax # sched: [1:0.25]
; X64-HSW-NEXT: imulq %rcx, %rax # sched: [4:1.00]
; X64-HSW-NEXT: imulq %rcx, %rax # sched: [3:1.00]
; X64-HSW-NEXT: retq # sched: [7:1.00]
;
; X64-JAG-LABEL: test_mul_spec:
@ -1840,7 +1840,7 @@ define i64 @test_mul_spec(i64 %x) nounwind {
; HSW-NOOPT-NEXT: addq $42, %rcx # sched: [1:0.25]
; HSW-NOOPT-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50]
; HSW-NOOPT-NEXT: addq $2, %rax # sched: [1:0.25]
; HSW-NOOPT-NEXT: imulq %rcx, %rax # sched: [4:1.00]
; HSW-NOOPT-NEXT: imulq %rcx, %rax # sched: [3:1.00]
; HSW-NOOPT-NEXT: retq # sched: [7:1.00]
;
; JAG-NOOPT-LABEL: test_mul_spec:

6
llvm/test/CodeGen/X86/recip-fastmath.ll
View File

@ -270,7 +270,7 @@ define float @f32_two_step(float %x) #2 {
; SKX: # %bb.0:
; SKX-NEXT: vrcpss %xmm0, %xmm0, %xmm1 # sched: [4:1.00]
; SKX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [5:0.50]
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:1.00]
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:0.33]
; SKX-NEXT: vfnmadd213ss %xmm2, %xmm0, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfmadd132ss %xmm1, %xmm1, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfnmadd213ss %xmm2, %xmm3, %xmm0 # sched: [4:0.33]
@ -535,7 +535,7 @@ define <4 x float> @v4f32_two_step(<4 x float> %x) #2 {
; SKX: # %bb.0:
; SKX-NEXT: vrcpps %xmm0, %xmm1 # sched: [4:1.00]
; SKX-NEXT: vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [6:0.50]
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:1.00]
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:0.33]
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm3, %xmm0 # sched: [4:0.33]
@ -823,7 +823,7 @@ define <8 x float> @v8f32_two_step(<8 x float> %x) #2 {
; SKX: # %bb.0:
; SKX-NEXT: vrcpps %ymm0, %ymm1 # sched: [4:1.00]
; SKX-NEXT: vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:1.00]
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:0.33]
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.33]
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm3 # sched: [4:0.33]
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm3, %ymm0 # sched: [4:0.33]

6
llvm/test/CodeGen/X86/recip-fastmath2.ll
View File

@ -382,7 +382,7 @@ define float @f32_two_step_2(float %x) #2 {
; SKX: # %bb.0:
; SKX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]
; SKX-NEXT: vrcpss %xmm0, %xmm0, %xmm2 # sched: [4:1.00]
; SKX-NEXT: vmovaps %xmm2, %xmm3 # sched: [1:1.00]
; SKX-NEXT: vmovaps %xmm2, %xmm3 # sched: [1:0.33]
; SKX-NEXT: vfnmadd213ss %xmm1, %xmm0, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfmadd132ss %xmm2, %xmm2, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfnmadd213ss %xmm1, %xmm3, %xmm0 # sched: [4:0.33]
@ -710,7 +710,7 @@ define <4 x float> @v4f32_two_step2(<4 x float> %x) #2 {
; SKX: # %bb.0:
; SKX-NEXT: vrcpps %xmm0, %xmm1 # sched: [4:1.00]
; SKX-NEXT: vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [6:0.50]
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:1.00]
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:0.33]
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm3 # sched: [4:0.33]
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm3, %xmm0 # sched: [4:0.33]
@ -1069,7 +1069,7 @@ define <8 x float> @v8f32_two_step2(<8 x float> %x) #2 {
; SKX: # %bb.0:
; SKX-NEXT: vrcpps %ymm0, %ymm1 # sched: [4:1.00]
; SKX-NEXT: vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:1.00]
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:0.33]
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.33]
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm3 # sched: [4:0.33]
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm3, %ymm0 # sched: [4:0.33]

6
llvm/test/CodeGen/X86/sha-schedule.ll
View File

@ -219,11 +219,11 @@ define <4 x i32> @test_sha256rnds2(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2,
;
; CANNONLAKE-LABEL: test_sha256rnds2:
; CANNONLAKE: # %bb.0:
; CANNONLAKE-NEXT: vmovaps %xmm0, %xmm3 # sched: [1:1.00]
; CANNONLAKE-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:1.00]
; CANNONLAKE-NEXT: vmovaps %xmm0, %xmm3 # sched: [1:0.33]
; CANNONLAKE-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:0.33]
; CANNONLAKE-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3 # sched: [5:1.00]
; CANNONLAKE-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm3 # sched: [10:1.00]
; CANNONLAKE-NEXT: vmovaps %xmm3, %xmm0 # sched: [1:1.00]
; CANNONLAKE-NEXT: vmovaps %xmm3, %xmm0 # sched: [1:0.33]
; CANNONLAKE-NEXT: retq # sched: [7:1.00]
;
; ZNVER1-LABEL: test_sha256rnds2:

2
llvm/test/CodeGen/X86/sse-schedule.ll
View File

@ -2134,7 +2134,7 @@ define <4 x float> @test_movss_reg(<4 x float> %a0, <4 x float> %a1) {
;
; SKX-LABEL: test_movss_reg:
; SKX: # %bb.0:
; SKX-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:1.00]
; SKX-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_movss_reg: