forked from OSchip/llvm-project
AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite loops.
Summary: The current StructurizeCFG pass only works for CFG with one exit. AMDGPUUnifyDivergentExitNodes combines multiple "return" blocks and/or "unreachable" blocks to one exit block for the Structurizer to work. However, infinite loop is another kind of special "exit", and if we don't handle it, the case of multiple exits will prevent the structurizer from working. In this work, for each infinite loop, we add a dummy edge to the "return" block, and thus the AMDGPUUnifyDivergentExitNodes pass will work with infinite loops. This will make CFG with infinite loops be structurized. Reviewer: nhaehnle Differential Revision: https://reviews.llvm.org/D46340 llvm-svn: 332625
This commit is contained in:
Changpeng Fang
parent
daf5169398
commit
391bcf8893
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@ -170,6 +170,9 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
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SmallVector<BasicBlock *, 4> ReturningBlocks;
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SmallVector<BasicBlock *, 4> UnreachableBlocks;
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// Dummy return block for infinite loop.
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BasicBlock *DummyReturnBB = nullptr;
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for (BasicBlock *BB : PDT.getRoots()) {
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if (isa<ReturnInst>(BB->getTerminator())) {
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if (!isUniformlyReached(DA, *BB))
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@ -177,6 +180,35 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
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} else if (isa<UnreachableInst>(BB->getTerminator())) {
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if (!isUniformlyReached(DA, *BB))
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UnreachableBlocks.push_back(BB);
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} else if (BranchInst *BI = dyn_cast<BranchInst>(BB->getTerminator())) {
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ConstantInt *BoolTrue = ConstantInt::getTrue(F.getContext());
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if (DummyReturnBB == nullptr) {
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DummyReturnBB = BasicBlock::Create(F.getContext(),
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"DummyReturnBlock", &F);
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Type *RetTy = F.getReturnType();
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Value *RetVal = RetTy->isVoidTy() ? nullptr : UndefValue::get(RetTy);
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ReturnInst::Create(F.getContext(), RetVal, DummyReturnBB);
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ReturningBlocks.push_back(DummyReturnBB);
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}
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if (BI->isUnconditional()) {
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BasicBlock *LoopHeaderBB = BI->getSuccessor(0);
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BI->eraseFromParent(); // Delete the unconditional branch.
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// Add a new conditional branch with a dummy edge to the return block.
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BranchInst::Create(LoopHeaderBB, DummyReturnBB, BoolTrue, BB);
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} else { // Conditional branch.
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// Create a new transition block to hold the conditional branch.
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BasicBlock *TransitionBB = BasicBlock::Create(F.getContext(),
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"TransitionBlock", &F);
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// Move BI from BB to the new transition block.
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BI->removeFromParent();
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TransitionBB->getInstList().push_back(BI);
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// Create a branch that will always branch to the transition block.
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BranchInst::Create(TransitionBB, DummyReturnBB, BoolTrue, BB);
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}
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}
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}
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@ -431,11 +431,17 @@ endif:
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; si_mask_branch
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; GCN-LABEL: {{^}}analyze_mask_branch:
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; GCN: v_cmp_lt_f32_e32 vcc
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; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN: v_cmp_nlt_f32_e32 vcc
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; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN-NEXT: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]]
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; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]
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; GCN: [[FLOW]]: ; %Flow
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; GCN-NEXT: s_or_saveexec_b64 [[TEMP_MASK1:s\[[0-9]+:[0-9]+\]]], [[MASK]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]]
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; GCN-NEXT: ; mask branch [[RET:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop_body
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; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop_body
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; GCN: ;;#ASMSTART
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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@ -444,6 +450,7 @@ endif:
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: ;;#ASMEND
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; GCN: s_cbranch_vccz [[RET]]
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; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop_body
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; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
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@ -452,9 +459,7 @@ endif:
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; GCN-NEXT: s_subb_u32 vcc_hi, vcc_hi, 0
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; GCN-NEXT: s_setpc_b64 vcc
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; GCN-NEXT: [[RET]]: ; %ret
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; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]
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; GCN: buffer_store_dword
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; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @analyze_mask_branch() #0 {
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entry:
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@ -2,10 +2,11 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s
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; GCN-LABEL: {{^}}test_loop:
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; GCN: s_and_b64 vcc, exec, -1
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; GCN: [[LABEL:BB[0-9+]_[0-9]+]]: ; %for.body{{$}}
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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; GCN: s_branch [[LABEL]]
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; GCN: s_cbranch_vccnz [[LABEL]]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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@ -1,18 +1,167 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify %s | FileCheck -check-prefix=IR %s
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; SI-LABEL: {{^}}infinite_loop:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
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; SI: BB0_1:
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; SI: [[LOOP:BB[0-9]+_[0-9]+]]: ; %loop
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG]]
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; SI: s_branch BB0_1
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; SI: s_branch [[LOOP]]
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define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
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entry:
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br label %for.body
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br label %loop
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for.body: ; preds = %entry, %for.body
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loop:
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store i32 999, i32 addrspace(1)* %out, align 4
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br label %for.body
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br label %loop
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}
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; IR-LABEL: @infinite_loop_ret(
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; IR: br i1 %cond, label %loop, label %UnifiedReturnBlock
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; IR: loop:
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; IR: store i32 999, i32 addrspace(1)* %out, align 4
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; IR: br i1 true, label %loop, label %UnifiedReturnBlock
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; IR: UnifiedReturnBlock:
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; IR: ret void
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; SI-LABEL: {{^}}infinite_loop_ret:
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; SI: s_cbranch_execz [[RET:BB[0-9]+_[0-9]+]]
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
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; SI: [[LOOP:BB[0-9]+_[0-9]+]]: ; %loop
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; SI: s_and_b64 vcc, exec, -1
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG]]
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; SI: s_cbranch_vccnz [[LOOP]]
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; SI: [[RET]]: ; %UnifiedReturnBlock
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; SI: s_endpgm
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define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) {
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond = icmp eq i32 %tmp, 1
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br i1 %cond, label %loop, label %return
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loop:
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store i32 999, i32 addrspace(1)* %out, align 4
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br label %loop
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return:
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ret void
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}
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; IR-LABEL: @infinite_loops(
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; IR: br i1 undef, label %loop1, label %loop2
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; IR: loop1:
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; IR: store i32 999, i32 addrspace(1)* %out, align 4
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; IR: br i1 true, label %loop1, label %DummyReturnBlock
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; IR: loop2:
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; IR: store i32 888, i32 addrspace(1)* %out, align 4
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; IR: br i1 true, label %loop2, label %DummyReturnBlock
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; IR: DummyReturnBlock:
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; IR: ret void
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; SI-LABEL: {{^}}infinite_loops:
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; SI: v_mov_b32_e32 [[REG1:v[0-9]+]], 0x3e7
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; SI: s_and_b64 vcc, exec, -1
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; SI: [[LOOP1:BB[0-9]+_[0-9]+]]: ; %loop1
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG1]]
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; SI: s_cbranch_vccnz [[LOOP1]]
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; SI: s_branch [[RET:BB[0-9]+_[0-9]+]]
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; SI: v_mov_b32_e32 [[REG2:v[0-9]+]], 0x378
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; SI: s_and_b64 vcc, exec, -1
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; SI: [[LOOP2:BB[0-9]+_[0-9]+]]: ; %loop2
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG2]]
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; SI: s_cbranch_vccnz [[LOOP2]]
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; SI: [[RET]]: ; %DummyReturnBlock
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; SI: s_endpgm
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define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
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entry:
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br i1 undef, label %loop1, label %loop2
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loop1:
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store i32 999, i32 addrspace(1)* %out, align 4
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br label %loop1
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loop2:
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store i32 888, i32 addrspace(1)* %out, align 4
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br label %loop2
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}
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; IR-LABEL: @infinite_loop_nest_ret(
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; IR: br i1 %cond1, label %outer_loop, label %UnifiedReturnBlock
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; IR: outer_loop:
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; IR: br label %inner_loop
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; IR: inner_loop:
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; IR: store i32 999, i32 addrspace(1)* %out, align 4
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; IR: %cond3 = icmp eq i32 %tmp, 3
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; IR: br i1 true, label %TransitionBlock, label %UnifiedReturnBlock
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; IR: TransitionBlock:
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; IR: br i1 %cond3, label %inner_loop, label %outer_loop
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; IR: UnifiedReturnBlock:
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; IR: ret void
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; SI-LABEL: {{^}}infinite_loop_nest_ret:
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; SI: s_cbranch_execz [[RET:BB[0-9]+_[0-9]+]]
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; SI: s_mov_b32
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; SI: [[OUTER_LOOP:BB[0-9]+_[0-9]+]]: ; %outer_loop
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; SI: [[INNER_LOOP:BB[0-9]+_[0-9]+]]: ; %inner_loop
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; SI: s_waitcnt expcnt(0)
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
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; SI: v_cmp_ne_u32_e32
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG]]
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; SI: s_andn2_b64 exec
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; SI: s_cbranch_execnz [[INNER_LOOP]]
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; SI: s_andn2_b64 exec
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; SI: s_cbranch_execnz [[OUTER_LOOP]]
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; SI: [[RET]]: ; %UnifiedReturnBlock
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; SI: s_endpgm
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define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) {
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond1 = icmp eq i32 %tmp, 1
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br i1 %cond1, label %outer_loop, label %return
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outer_loop:
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; %cond2 = icmp eq i32 %tmp, 2
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; br i1 %cond2, label %outer_loop, label %inner_loop
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br label %inner_loop
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inner_loop: ; preds = %LeafBlock, %LeafBlock1
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store i32 999, i32 addrspace(1)* %out, align 4
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%cond3 = icmp eq i32 %tmp, 3
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br i1 %cond3, label %inner_loop, label %outer_loop
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return:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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@ -70,7 +70,7 @@
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; GCN: [[BB9:BB[0-9]+_[0-9]+]]: ; %bb9
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_branch [[BB9]]
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; GCN-NEXT: s_cbranch_vccnz [[BB9]]
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define amdgpu_kernel void @reduced_nested_loop_conditions(i64 addrspace(3)* nocapture %arg) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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@ -96,7 +96,7 @@ declare float @llvm.fabs.f32(float) nounwind readnone
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; SI-NEXT: s_cbranch_scc1 [[ENDPGM]]
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; SI: [[INFLOOP:BB[0-9]+_[0-9]+]]
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; SI: s_branch [[INFLOOP]]
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; SI: s_cbranch_vccnz [[INFLOOP]]
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; SI: [[ENDPGM]]:
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; SI: s_endpgm
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