maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer. 

llvm-svn: 28984
This commit is contained in:
Evan Cheng 2006-06-29 18:04:54 +00:00
parent 3aa5a4bf61
commit 390922f979
1 changed files with 10 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -2109,15 +2109,9 @@ def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
"pxor $dst, $dst",
[(set VR128:$dst, (v2i64 immAllZerosV))]>;
def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
"xorps $dst, $dst",
[(set VR128:$dst, (v4f32 immAllZerosV))]>;
def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
"xorps $dst, $dst",
[(set VR128:$dst, (v2f64 immAllZerosV))]>;
def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
"xorps $dst, $dst",
[(set VR128:$dst, (v4f32 immAllZerosV))]>;
def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
"pcmpeqd $dst, $dst",
@ -2265,9 +2259,11 @@ def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
// 128-bit vector all zero's.
def : Pat<(v16i8 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>;
def : Pat<(v8i16 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>;
def : Pat<(v4i32 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>;
def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
// 128-bit vector all one's.
def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
@ -2365,10 +2361,10 @@ def : Pat<(v16i8 (vector_shuffle immAllZerosV,
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
def : Pat<(v2f64 (vector_shuffle immAllZerosV,
(v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
(MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
(MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
def : Pat<(v4f32 (vector_shuffle immAllZerosV,
(v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
(MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
(MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
}
// Splat v2f64 / v2i64