forked from OSchip/llvm-project
LiveInterval: Add utility class to rename independent subregister usage
This renaming is necessary to avoid a subregister aware scheduler
accidentally creating liveness "holes" which are rejected by the
MachineVerifier.
Explanation as found in this patch:
Helper class that can divide MachineOperands of a virtual register into
equivalence classes of connected components.
MachineOperands belong to the same equivalence class when they are part of
the same SubRange segment or adjacent segments (adjacent in control
flow); Different subranges affected by the same MachineOperand belong to
the same equivalence class.
Example:
vreg0:sub0 = ...
vreg0:sub1 = ...
vreg0:sub2 = ...
...
xxx = op vreg0:sub1
vreg0:sub1 = ...
store vreg0:sub0_sub1
The example contains 3 different equivalence classes:
- One for the (dead) vreg0:sub2 definition
- One containing the first vreg0:sub1 definition and its use,
but not the second definition!
- The remaining class contains all other operands involving vreg0.
We provide a utility function here to rename disjunct classes to different
virtual registers.
Differential Revision: http://reviews.llvm.org/D16126
llvm-svn: 258257
This commit is contained in:
Matthias Braun
parent
2e045bbc5f
commit
3907fded1b
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@ -864,5 +864,74 @@ namespace llvm {
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MachineRegisterInfo &MRI);
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};
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/// Helper class that can divide MachineOperands of a virtual register into
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/// equivalence classes of connected components.
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/// MachineOperands belong to the same equivalence class when they are part of
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/// the same SubRange segment or adjacent segments (adjacent in control
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/// flow); Different subranges affected by the same MachineOperand belong to
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/// the same equivalence class.
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///
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/// Example:
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/// vreg0:sub0 = ...
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/// vreg0:sub1 = ...
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/// vreg0:sub2 = ...
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/// ...
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/// xxx = op vreg0:sub1
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/// vreg0:sub1 = ...
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/// store vreg0:sub0_sub1
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///
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/// The example contains 3 different equivalence classes:
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/// - One for the (dead) vreg0:sub2 definition
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/// - One containing the first vreg0:sub1 definition and its use,
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/// but not the second definition!
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/// - The remaining class contains all other operands involving vreg0.
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///
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/// We provide a utility function here to rename disjunct classes to different
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/// virtual registers.
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class ConnectedSubRegClasses {
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LiveIntervals &LIS;
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MachineRegisterInfo &MRI;
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public:
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ConnectedSubRegClasses(LiveIntervals &LIS, MachineRegisterInfo &MRI)
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: LIS(LIS), MRI(MRI) {}
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/// Split unrelated subregister components and rename them to new vregs.
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void renameComponents(LiveInterval &LI) const;
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private:
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struct SubRangeInfo {
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ConnectedVNInfoEqClasses ConEQ;
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LiveInterval::SubRange *SR;
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unsigned Index;
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SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR,
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unsigned Index)
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: ConEQ(LIS), SR(&SR), Index(Index) {}
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};
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/// \brief Build a vector of SubRange infos and a union find set of
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/// equivalence classes.
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/// Returns true if more than 1 equivalence class was found.
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bool findComponents(IntEqClasses &Classes,
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SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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LiveInterval &LI) const;
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/// \brief Distribute the LiveInterval segments into the new LiveIntervals
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/// belonging to their class.
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void distribute(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const;
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/// \brief Constructs main liverange and add missing undef+dead flags.
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void computeMainRangesFixFlags(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const;
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/// Rewrite Machine Operands to use the new vreg belonging to their class.
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void rewriteOperands(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const;
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};
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}
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#endif
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@ -406,6 +406,11 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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void splitSeparateComponents(LiveInterval &LI,
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SmallVectorImpl<LiveInterval*> &SplitLIs);
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/// Assure dead subregister definitions have their own vreg assigned.
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/// This calls ConnectedSubRegClasses::splitSeparateSubRegComponent()
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/// on each virtual register.
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void renameDisconnectedComponents();
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private:
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/// Compute live intervals for all virtual registers.
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void computeVirtRegs();
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@ -1466,3 +1466,186 @@ void ConnectedVNInfoEqClasses::Distribute(LiveInterval &LI, LiveInterval *LIV[],
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// Distribute main liverange.
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DistributeRange(LI, LIV, EqClass);
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}
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void ConnectedSubRegClasses::renameComponents(LiveInterval &LI) const {
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// Shortcut: We cannot have split components with a single definition.
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if (LI.valnos.size() < 2)
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return;
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SmallVector<SubRangeInfo, 4> SubRangeInfos;
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IntEqClasses Classes;
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if (!findComponents(Classes, SubRangeInfos, LI))
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return;
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// Create a new VReg for each class.
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unsigned Reg = LI.reg;
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const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
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SmallVector<LiveInterval*, 4> Intervals;
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Intervals.push_back(&LI);
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for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses;
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++I) {
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unsigned NewVReg = MRI.createVirtualRegister(RegClass);
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LiveInterval &NewLI = LIS.createEmptyInterval(NewVReg);
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Intervals.push_back(&NewLI);
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}
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rewriteOperands(Classes, SubRangeInfos, Intervals);
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distribute(Classes, SubRangeInfos, Intervals);
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computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals);
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}
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bool ConnectedSubRegClasses::findComponents(IntEqClasses &Classes,
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SmallVectorImpl<ConnectedSubRegClasses::SubRangeInfo> &SubRangeInfos,
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LiveInterval &LI) const {
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// First step: Create connected components for the VNInfos inside the
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// subranges and count the global number of such components.
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unsigned NumComponents = 0;
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for (LiveInterval::SubRange &SR : LI.subranges()) {
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SubRangeInfos.push_back(SubRangeInfo(LIS, SR, NumComponents));
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ConnectedVNInfoEqClasses &ConEQ = SubRangeInfos.back().ConEQ;
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unsigned NumSubComponents = ConEQ.Classify(SR);
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NumComponents += NumSubComponents;
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}
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// Shortcut: With only 1 subrange, the normal separate component tests are
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// enough and we do not need to perform the union-find on the subregister
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// segments.
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if (SubRangeInfos.size() < 2)
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return false;
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// Next step: Build union-find structure over all subranges and merge classes
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// across subranges when they are affected by the same MachineOperand.
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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Classes.grow(NumComponents);
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unsigned Reg = LI.reg;
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for (const MachineOperand &MO : MRI.reg_nodbg_operands(Reg)) {
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if (!MO.isDef() && !MO.readsReg())
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continue;
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unsigned SubRegIdx = MO.getSubReg();
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LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
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unsigned MergedID = ~0u;
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for (auto &SRInfo : SubRangeInfos) {
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const LiveInterval::SubRange &SR = *SRInfo.SR;
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if ((SR.LaneMask & LaneMask) == 0)
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continue;
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SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
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Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
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: Pos.getBaseIndex();
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const VNInfo *VNI = SR.getVNInfoAt(Pos);
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if (VNI == nullptr)
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continue;
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// Map to local representant ID.
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unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
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// Global ID
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unsigned ID = LocalID + SRInfo.Index;
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// Merge other sets
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MergedID = MergedID == ~0u ? ID : Classes.join(MergedID, ID);
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}
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}
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// Early exit if we ended up with a single equivalence class.
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Classes.compress();
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unsigned NumClasses = Classes.getNumClasses();
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return NumClasses > 1;
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}
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void ConnectedSubRegClasses::rewriteOperands(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const {
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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unsigned Reg = Intervals[0]->reg;;
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for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(Reg),
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E = MRI.reg_nodbg_end(); I != E; ) {
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MachineOperand &MO = *I++;
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if (!MO.isDef() && !MO.readsReg())
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continue;
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MachineInstr &MI = *MO.getParent();
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SlotIndex Pos = LIS.getInstructionIndex(&MI);
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unsigned SubRegIdx = MO.getSubReg();
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LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
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unsigned ID = ~0u;
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for (auto &SRInfo : SubRangeInfos) {
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const LiveInterval::SubRange &SR = *SRInfo.SR;
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if ((SR.LaneMask & LaneMask) == 0)
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continue;
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LiveRange::const_iterator I = SR.find(Pos);
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if (I == SR.end())
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continue;
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const VNInfo &VNI = *I->valno;
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// Map to local representant ID.
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unsigned LocalID = SRInfo.ConEQ.getEqClass(&VNI);
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// Global ID
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ID = Classes[LocalID + SRInfo.Index];
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break;
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}
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unsigned VReg = Intervals[ID]->reg;
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MO.setReg(VReg);
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}
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}
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void ConnectedSubRegClasses::distribute(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const {
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unsigned NumClasses = Classes.getNumClasses();
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SmallVector<unsigned, 8> VNIMapping;
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SmallVector<LiveInterval::SubRange*, 8> SubRanges;
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BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
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for (auto &SRInfo : SubRangeInfos) {
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LiveInterval::SubRange &SR = *SRInfo.SR;
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unsigned NumValNos = SR.valnos.size();
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VNIMapping.clear();
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VNIMapping.reserve(NumValNos);
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SubRanges.clear();
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SubRanges.resize(NumClasses-1, nullptr);
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for (unsigned I = 0; I < NumValNos; ++I) {
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const VNInfo &VNI = *SR.valnos[I];
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unsigned LocalID = SRInfo.ConEQ.getEqClass(&VNI);
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unsigned ID = Classes[LocalID + SRInfo.Index];
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VNIMapping.push_back(ID);
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if (ID > 0 && SubRanges[ID-1] == nullptr)
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SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask);
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}
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DistributeRange(SR, SubRanges.data(), VNIMapping);
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}
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}
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void ConnectedSubRegClasses::computeMainRangesFixFlags(
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const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const {
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BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
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for (size_t I = 0, E = Intervals.size(); I < E; ++I) {
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LiveInterval *LI = Intervals[I];
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LI->removeEmptySubRanges();
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if (I == 0)
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LI->clear();
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LI->constructMainRangeFromSubranges(*LIS.getSlotIndexes(), Allocator);
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for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
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if (!MO.isDef())
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continue;
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unsigned SubRegIdx = MO.getSubReg();
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if (SubRegIdx == 0)
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continue;
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// After assigning the new vreg we may not have any other sublanes living
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// in and out of the instruction anymore. We need to add new dead and kill
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// flags in these cases.
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if (!MO.isUndef()) {
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SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
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if (!LI->liveAt(Pos.getBaseIndex()))
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MO.setIsUndef();
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}
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if (!MO.isDead()) {
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SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
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if (!LI->liveAt(Pos.getDeadSlot()))
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MO.setIsDead();
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}
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}
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}
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}
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@ -1459,3 +1459,19 @@ void LiveIntervals::splitSeparateComponents(LiveInterval &LI,
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}
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ConEQ.Distribute(LI, SplitLIs.data(), *MRI);
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}
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void LiveIntervals::renameDisconnectedComponents() {
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ConnectedSubRegClasses SubRegClasses(*this, *MRI);
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// Iterate over all vregs. Note that we query getNumVirtRegs() the newly
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// created vregs end up with higher numbers but do not need to be visited as
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// there can't be any further splitting.
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for (size_t I = 0, E = MRI->getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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LiveInterval *LI = VirtRegIntervals[Reg];
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if (LI == nullptr || !LI->hasSubRanges())
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continue;
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SubRegClasses.renameComponents(*LI);
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}
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}
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