forked from OSchip/llvm-project
AMDGPU/GlobalISel: Fix test failure in release build
The annoying behavior where the output is different due to the legality check struck again, plus the subtarget predicate wasn't really correctly set for DS FP atomics. Some of the FP min/max instructions seem to be in the gfx6/gfx7 manuals, but IIRC this might have been one of the cases where the manual got ahead of the actual hardware support, but I've left these as-is for now since the assembler tests seem to expect them.
This commit is contained in:
Matt Arsenault
parent
f14d4c9c54
commit
38fb446fc7
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@ -1048,6 +1048,9 @@ def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
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def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
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AssemblerPredicate<(all_of FeatureGFX9Insts)>;
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def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
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AssemblerPredicate<(all_of FeatureGFX8Insts)>;
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def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
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AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
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@ -388,7 +388,12 @@ defm DS_MAX_U32 : DS_1A1D_NORET_mc<"ds_max_u32">;
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defm DS_AND_B32 : DS_1A1D_NORET_mc<"ds_and_b32">;
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defm DS_OR_B32 : DS_1A1D_NORET_mc<"ds_or_b32">;
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defm DS_XOR_B32 : DS_1A1D_NORET_mc<"ds_xor_b32">;
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let SubtargetPredicate = HasLDSFPAtomics in {
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defm DS_ADD_F32 : DS_1A1D_NORET_mc<"ds_add_f32">;
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}
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// FIXME: Are these really present pre-gfx8?
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defm DS_MIN_F32 : DS_1A1D_NORET_mc<"ds_min_f32">;
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defm DS_MAX_F32 : DS_1A1D_NORET_mc<"ds_max_f32">;
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@ -443,7 +448,10 @@ defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
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defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
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defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
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let SubtargetPredicate = HasLDSFPAtomics in {
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defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
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}
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defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
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defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
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defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
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@ -609,10 +617,12 @@ def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
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int_amdgcn_ds_bpermute>;
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}
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def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
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} // let SubtargetPredicate = isGFX8Plus
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let SubtargetPredicate = HasLDSFPAtomics in {
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def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
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}
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//===----------------------------------------------------------------------===//
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// DS Patterns
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//===----------------------------------------------------------------------===//
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@ -830,9 +840,12 @@ defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
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defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
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defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
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defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
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let SubtargetPredicate = HasLDSFPAtomics in {
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defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
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defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
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defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
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}
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// 64-bit atomics.
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defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
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@ -1,10 +1,11 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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# GFX6/7 selection should fail.
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s
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---
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name: atomicrmw_fadd_s32_local
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@ -15,12 +16,6 @@ body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
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; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
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; GFX8-LABEL: name: atomicrmw_fadd_s32_local
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; GFX8: liveins: $vgpr0, $vgpr1
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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@ -34,6 +29,13 @@ body: |
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
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; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst 4, addrspace 3)
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@ -50,11 +52,6 @@ body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local_noret
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
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; GFX8-LABEL: name: atomicrmw_fadd_s32_local_noret
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; GFX8: liveins: $vgpr0, $vgpr1
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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@ -66,6 +63,12 @@ body: |
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local_noret
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst 4, addrspace 3)
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@ -81,14 +84,6 @@ body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local_gep4
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX6: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 4
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; GFX6: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
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; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[PTR_ADD]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
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; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
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; GFX8-LABEL: name: atomicrmw_fadd_s32_local_gep4
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; GFX8: liveins: $vgpr0, $vgpr1
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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@ -102,6 +97,15 @@ body: |
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 4, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local_gep4
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX6: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 4
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; GFX6: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[PTR_ADD]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
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; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_CONSTANT i32 4
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