forked from OSchip/llvm-project
Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."
Previously reverted by r267752. r267733 review: Differential Revision: http://reviews.llvm.org/D19342 llvm-svn: 268066
This commit is contained in:
Artem Tamazov
parent
e801f6a7f4
commit
38e496b175
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@ -644,13 +644,14 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) {
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default: return -1;
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case 1: return AMDGPU::TTMP_32RegClassID;
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case 2: return AMDGPU::TTMP_64RegClassID;
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case 4: return AMDGPU::TTMP_128RegClassID;
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}
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} else if (Is == IS_SGPR) {
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switch (RegWidth) {
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default: return -1;
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case 1: return AMDGPU::SGPR_32RegClassID;
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case 2: return AMDGPU::SGPR_64RegClassID;
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case 4: return AMDGPU::SReg_128RegClassID;
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case 4: return AMDGPU::SGPR_128RegClassID;
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case 8: return AMDGPU::SReg_256RegClassID;
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case 16: return AMDGPU::SReg_512RegClassID;
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}
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@ -66,8 +66,8 @@ DECODE_OPERAND(VReg_64)
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DECODE_OPERAND(VReg_96)
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DECODE_OPERAND(VReg_128)
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DECODE_OPERAND(SGPR_32)
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DECODE_OPERAND(SReg_32)
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DECODE_OPERAND(SReg_32_XM0)
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DECODE_OPERAND(SReg_64)
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DECODE_OPERAND(SReg_128)
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DECODE_OPERAND(SReg_256)
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@ -237,10 +237,6 @@ MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
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return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SGPR_32(unsigned Val) const {
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return createSRegOperand(AMDGPU::SGPR_32RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
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// table-gen generated disassembler doesn't care about operand types
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// leaving only registry class so SSrc_32 operand turns into SReg_32
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@ -248,6 +244,11 @@ MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
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return decodeSrcOp(OP32, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const {
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// SReg_32_XM0 is SReg_32 without M0
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return decodeOperand_SReg_32(Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
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// see decodeOperand_SReg_32 comment
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return decodeSrcOp(OP64, Val);
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@ -62,8 +62,8 @@ namespace llvm {
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MCOperand decodeOperand_VReg_96(unsigned Val) const;
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MCOperand decodeOperand_VReg_128(unsigned Val) const;
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MCOperand decodeOperand_SGPR_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
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MCOperand decodeOperand_SReg_64(unsigned Val) const;
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MCOperand decodeOperand_SReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_256(unsigned Val) const;
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@ -250,9 +250,12 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
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} else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
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Type = "v";
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NumRegs = 4;
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} else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
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} else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(reg)) {
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Type = "s";
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NumRegs = 4;
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} else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(reg)) {
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Type = "ttmp";
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NumRegs = 4;
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} else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
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Type = "v";
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NumRegs = 3;
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@ -60,17 +60,17 @@ defm EXP : EXP_m;
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// SMRD Instructions
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//===----------------------------------------------------------------------===//
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// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
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// SMRD instructions, because the SGPR_32 register class does not include M0
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// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
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// SMRD instructions, because the SReg_32_XM0 register class does not include M0
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// and writing to M0 from an SMRD instruction will hang the GPU.
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defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>;
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defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SReg_32_XM0>;
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defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;
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defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
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defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;
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defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;
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defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
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smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32
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smrd<0x08>, "s_buffer_load_dword", SReg_128, SReg_32_XM0
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>;
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defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
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@ -2087,9 +2087,9 @@ multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
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}
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// It's unclear whether you can use M0 as the output of v_readlane_b32
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// instructions, so use SGPR_32 register class for spills to prevent
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// instructions, so use SReg_32_XM0 register class for spills to prevent
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// this from happening.
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defm SI_SPILL_S32 : SI_SPILL_SGPR <SGPR_32>;
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defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32_XM0>;
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defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
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defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
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defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
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@ -3431,7 +3431,7 @@ def : ZExt_i64_i1_Pat<anyext>;
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def : Pat <
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(i64 (sext i32:$src)),
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(REG_SEQUENCE SReg_64, $src, sub0,
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(i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SGPR_32)), sub1)
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(i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SReg_32_XM0)), sub1)
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>;
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def : Pat <
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@ -132,7 +132,7 @@ def SGPR_64Regs : RegisterTuples<[sub0, sub1],
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(add (decimate (shl SGPR_32, 1), 2))]>;
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// SGPR 128-bit registers
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def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
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def SGPR_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
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[(add (decimate SGPR_32, 4)),
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(add (decimate (shl SGPR_32, 1), 4)),
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(add (decimate (shl SGPR_32, 2), 4)),
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@ -255,6 +255,13 @@ def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
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TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)
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>;
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// Subset of SReg_32 without M0 for SMRD instructions and alike.
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// See comments in SIInstructions.td for more info.
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def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32,
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(add SGPR_32, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
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TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)
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>;
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def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>;
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def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
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@ -265,11 +272,19 @@ def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
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(add SGPR_64, VCC, EXEC, FLAT_SCR, TTMP_64, TBA, TMA)
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>;
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def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128)> {
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// Requires 2 s_mov_b64 to copy
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let CopyCost = 2;
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// Requires 2 s_mov_b64 to copy
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let CopyCost = 2 in {
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def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)>;
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def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> {
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let isAllocatable = 0;
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}
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def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128, TTMP_128)>;
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} // End CopyCost = 2
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def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {
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// Requires 4 s_mov_b64 to copy
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let CopyCost = 4;
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@ -18,6 +18,10 @@ buffer_load_dword v1, off, s[4:7], s1
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// SICI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
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// VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
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buffer_load_dword v1, off, ttmp[4:7], s1
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// SICI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x01]
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// VI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x01]
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buffer_load_dword v1, off, s[4:7], s1 offset:4
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// SICI: buffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
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// VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
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@ -42,6 +46,10 @@ buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01]
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// VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x81,0x01]
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buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xdd,0x01]
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// VI: buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x9d,0x01]
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//===----------------------------------------------------------------------===//
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// load - vgpr offset
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//===----------------------------------------------------------------------===//
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@ -74,6 +82,10 @@ buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01]
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// VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52,0xe0,0x02,0x01,0x81,0x01]
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buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xdd,0x01]
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// VI: buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52,0xe0,0x02,0x01,0x9d,0x01]
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//===----------------------------------------------------------------------===//
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// load - vgpr index
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//===----------------------------------------------------------------------===//
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@ -106,6 +118,10 @@ buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01]
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// VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52,0xe0,0x02,0x01,0x81,0x01]
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buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xdd,0x01]
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// VI: buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52,0xe0,0x02,0x01,0x9d,0x01]
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//===----------------------------------------------------------------------===//
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// load - vgpr index and offset
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//===----------------------------------------------------------------------===//
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@ -138,6 +154,10 @@ buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01]
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// VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x52,0xe0,0x02,0x01,0x81,0x01]
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buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xdd,0x71]
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// VI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x52,0xe0,0x02,0x01,0x9d,0x71]
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//===----------------------------------------------------------------------===//
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// load - addr64
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//===----------------------------------------------------------------------===//
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@ -170,6 +190,10 @@ buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01]
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// NOVI: error: instruction not supported on this GPU
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buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe
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// SICI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xdd,0x71]
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// NOVI: error: instruction not supported on this GPU
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//===----------------------------------------------------------------------===//
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// store - immediate offset only
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//===----------------------------------------------------------------------===//
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@ -202,6 +226,10 @@ buffer_store_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
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// SICI: buffer_store_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01]
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// VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x81,0x01]
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buffer_store_dword v1, off, ttmp[4:7], ttmp1 offset:4 glc slc tfe
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// SICI: buffer_store_dword v1, off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xdd,0x71]
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// VI: buffer_store_dword v1, off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x9d,0x71]
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//===----------------------------------------------------------------------===//
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// store - vgpr offset
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//===----------------------------------------------------------------------===//
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@ -234,6 +262,10 @@ buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
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// SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01]
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// VI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x81,0x01]
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buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe
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// SICI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xdd,0x71]
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// VI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x9d,0x71]
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//===----------------------------------------------------------------------===//
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// store - vgpr index
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//===----------------------------------------------------------------------===//
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@ -266,6 +298,10 @@ buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
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// SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01]
|
||||
// VI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x81,0x01]
|
||||
|
||||
buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe
|
||||
// SICI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xdd,0x71]
|
||||
// VI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x9d,0x71]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// store - vgpr index and offset
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -298,6 +334,10 @@ buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe
|
|||
// SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01]
|
||||
// VI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x81,0x01]
|
||||
|
||||
buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe
|
||||
// SICI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xdd,0x71]
|
||||
// VI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x9d,0x71]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// store - addr64
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -330,6 +370,10 @@ buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe
|
|||
// SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe
|
||||
// SICI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xdd,0x71]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -366,10 +410,18 @@ buffer_store_format_xyzw v[1:4], off, s[4:7], s1
|
|||
// SICI: buffer_store_format_xyzw v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_store_format_xyzw v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
||||
buffer_store_format_xyzw v[1:4], off, ttmp[4:7], ttmp1
|
||||
// SICI: buffer_store_format_xyzw v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_store_format_xyzw v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
buffer_load_ubyte v1, off, s[4:7], s1
|
||||
// SICI: buffer_load_ubyte v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_load_ubyte v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
||||
buffer_load_ubyte v1, off, ttmp[4:7], ttmp1
|
||||
// SICI: buffer_load_ubyte v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_load_ubyte v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
buffer_load_sbyte v1, off, s[4:7], s1
|
||||
// SICI: buffer_load_sbyte v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_load_sbyte v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x44,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
|
@ -386,6 +438,10 @@ buffer_load_dword v1, off, s[4:7], s1
|
|||
// SICI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
||||
buffer_load_dword v1, off, ttmp[4:7], ttmp1
|
||||
// SICI: buffer_load_dword v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_load_dword v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
buffer_load_dwordx2 v[1:2], off, s[4:7], s1
|
||||
// SICI: buffer_load_dwordx2 v[1:2], off, s[4:7], s1 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_load_dwordx2 v[1:2], off, s[4:7], s1 ; encoding: [0x00,0x00,0x54,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
|
@ -394,10 +450,18 @@ buffer_load_dwordx4 v[1:4], off, s[4:7], s1
|
|||
// SICI: buffer_load_dwordx4 v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_load_dwordx4 v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
||||
buffer_load_dwordx4 v[1:4], off, ttmp[4:7], ttmp1
|
||||
// SICI: buffer_load_dwordx4 v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_load_dwordx4 v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
buffer_store_byte v1, off, s[4:7], s1
|
||||
// SICI: buffer_store_byte v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_store_byte v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
||||
buffer_store_byte v1, off, ttmp[4:7], ttmp1
|
||||
// SICI: buffer_store_byte v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_store_byte v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
buffer_store_short v1, off, s[4:7], s1
|
||||
// SICI: buffer_store_short v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_store_short v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
|
@ -414,6 +478,10 @@ buffer_store_dwordx4 v[1:4], off, s[4:7], s1
|
|||
// SICI: buffer_store_dwordx4 v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_store_dwordx4 v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
||||
buffer_store_dwordx4 v[1:4], off, ttmp[4:7], ttmp1
|
||||
// SICI: buffer_store_dwordx4 v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_store_dwordx4 v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Cache invalidation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -53,3 +53,31 @@ v_rcp_f64 [v1,v2], [v2,v3]
|
|||
buffer_load_dwordx4 [v1,v2,v3,v4], off, [s4,s5,s6,s7], s1
|
||||
// SICI: buffer_load_dwordx4 v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01]
|
||||
// VI: buffer_load_dwordx4 v[1:4], off, s[4:7], s1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x01,0x01]
|
||||
|
||||
buffer_load_dword v1, off, [ttmp4,ttmp5,ttmp6,ttmp7], s1
|
||||
// SICI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x01]
|
||||
// VI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x01]
|
||||
|
||||
buffer_store_format_xyzw v[1:4], off, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1
|
||||
// SICI: buffer_store_format_xyzw v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_store_format_xyzw v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
buffer_load_ubyte v1, off, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1
|
||||
// SICI: buffer_load_ubyte v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_load_ubyte v1, off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
buffer_store_dwordx4 v[1:4], off, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1
|
||||
// SICI: buffer_store_dwordx4 v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x1d,0x71]
|
||||
// VI: buffer_store_dwordx4 v[1:4], off, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x1d,0x71]
|
||||
|
||||
s_load_dwordx4 [ttmp4,ttmp5,ttmp6,ttmp7], [ttmp2,ttmp3], ttmp4
|
||||
// SICI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x74,0x72,0xba,0xc0]
|
||||
// VI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x39,0x1d,0x08,0xc0,0x74,0x00,0x00,0x00]
|
||||
|
||||
s_buffer_load_dword ttmp1, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
|
||||
// SICI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]
|
||||
// VI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x7a,0x1c,0x20,0xc0,0x74,0x00,0x00,0x00]
|
||||
|
||||
s_buffer_load_dwordx4 [ttmp8,ttmp9,ttmp10,ttmp11], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
|
||||
// SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
|
||||
// VI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
|
||||
|
|
|
|||
|
|
@ -52,6 +52,10 @@ s_load_dwordx4 s[4:7], s[2:3], s4
|
|||
// GCN: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]
|
||||
// VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
|
||||
|
||||
s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4
|
||||
// GCN: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x74,0x72,0xba,0xc0]
|
||||
// VI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x39,0x1d,0x08,0xc0,0x74,0x00,0x00,0x00]
|
||||
|
||||
s_load_dwordx4 s[100:103], s[2:3], s4
|
||||
// GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]
|
||||
// NOVI: error: invalid operand for instruction
|
||||
|
|
@ -88,6 +92,10 @@ s_buffer_load_dword s1, s[4:7], s4
|
|||
// GCN: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x04,0x84,0x00,0xc2]
|
||||
// VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]
|
||||
|
||||
s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4
|
||||
// GCN: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]
|
||||
// VI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x7a,0x1c,0x20,0xc0,0x74,0x00,0x00,0x00]
|
||||
|
||||
s_buffer_load_dwordx2 s[8:9], s[4:7], 1
|
||||
// GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x01,0x05,0x44,0xc2]
|
||||
// VI: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x02,0x02,0x26,0xc0,0x01,0x00,0x00,0x00]
|
||||
|
|
@ -104,6 +112,10 @@ s_buffer_load_dwordx4 s[8:11], s[4:7], s4
|
|||
// GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x04,0x04,0x84,0xc2]
|
||||
// VI: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x02,0x02,0x28,0xc0,0x04,0x00,0x00,0x00]
|
||||
|
||||
s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4
|
||||
// GCN: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
|
||||
// VI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
|
||||
|
||||
s_buffer_load_dwordx4 s[100:103], s[4:7], s4
|
||||
// GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]
|
||||
// NOVI: error: invalid operand for instruction
|
||||
|
|
|
|||
Loading…
Reference in New Issue