forked from OSchip/llvm-project
[RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines
This target-independent code won't trigger for cases such as RV32FD where custom SelectionDAG nodes are generated. These new tests demonstrate such cases. Additionally, float-arith.ll was updated so that fneg.s, fsgnjn.s, and fabs.s selection patterns are actually exercised. llvm-svn: 352199
This commit is contained in:
Alex Bradbury
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@ -0,0 +1,80 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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;
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; This file tests cases where simple floating point operations can be
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; profitably handled though bit manipulation if a soft-float ABI is being used
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; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
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; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
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; in cases where we perform custom legalisation (e.g. RV32IFD).
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; TODO: Add an appropriate target-specific DAG combine that can handle
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; RISCVISD::SplitF64/BuildPairF64 used for RV32IFD.
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define double @fneg(double %a) nounwind {
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; RV32I-LABEL: fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV32IFD-LABEL: fneg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fneg.d ft0, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64I-LABEL: fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a1, zero, -1
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; RV64I-NEXT: slli a1, a1, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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%1 = fneg double %a
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ret double %1
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}
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declare double @llvm.fabs.f64(double)
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define double @fabs(double %a) nounwind {
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; RV32I-LABEL: fabs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: addi a2, a2, -1
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; RV32I-NEXT: and a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV32IFD-LABEL: fabs:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fabs.d ft0, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64I-LABEL: fabs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a1, zero, -1
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; RV64I-NEXT: slli a1, a1, 63
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; RV64I-NEXT: addi a1, a1, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%1 = call double @llvm.fabs.f64(double %a)
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ret double %1
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}
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@ -81,50 +81,58 @@ define float @fsgnj_s(float %a, float %b) nounwind {
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ret float %1
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}
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define float @fneg_s(float %a) nounwind {
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; TODO: doesn't test the fneg selection pattern because
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; DAGCombiner::visitBITCAST will generate a xor on the incoming integer
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; argument
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
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define i32 @fneg_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fneg_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a1, 524288
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; RV32IF-NEXT: xor a0, a0, a1
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fadd.s ft0, ft0, ft0
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; RV32IF-NEXT: fneg.s ft1, ft0
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; RV32IF-NEXT: feq.s a0, ft0, ft1
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; RV32IF-NEXT: ret
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%1 = fsub float -0.0, %a
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ret float %1
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%1 = fadd float %a, %a
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%2 = fneg float %1
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%3 = fcmp oeq float %1, %2
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%4 = zext i1 %3 to i32
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ret i32 %4
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}
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
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define float @fsgnjn_s(float %a, float %b) nounwind {
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; TODO: fsgnjn.s isn't selected because DAGCombiner::visitBITCAST will convert
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; (bitconvert (fneg x)) to a xor
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; RV32IF-LABEL: fsgnjn_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a2, 524288
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; RV32IF-NEXT: xor a1, a1, a2
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fsgnjn.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fsub float -0.0, %b
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%2 = call float @llvm.copysign.f32(float %a, float %1)
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ret float %2
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%1 = fadd float %a, %b
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%2 = fneg float %1
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%3 = call float @llvm.copysign.f32(float %a, float %2)
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ret float %3
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}
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declare float @llvm.fabs.f32(float)
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define float @fabs_s(float %a) nounwind {
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; TODO: doesn't test the fabs selection pattern because
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; DAGCombiner::visitBITCAST will generate an and on the incoming integer
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; argument
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
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define float @fabs_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fabs_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a1, 524288
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; RV32IF-NEXT: addi a1, a1, -1
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; RV32IF-NEXT: and a0, a0, a1
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fabs.s ft1, ft0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = call float @llvm.fabs.f32(float %a)
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ret float %1
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%1 = fadd float %a, %b
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%2 = call float @llvm.fabs.f32(float %1)
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%3 = fadd float %2, %1
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ret float %3
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}
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declare float @llvm.minnum.f32(float, float)
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@ -0,0 +1,49 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; This file tests cases where simple floating point operations can be
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; profitably handled though bit manipulation if a soft-float ABI is being used
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; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
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; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
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; in cases where we perform custom legalisation (e.g. RV64F).
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define float @fneg(float %a) nounwind {
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; RV32I-LABEL: fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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%1 = fneg float %a
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ret float %1
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}
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declare float @llvm.fabs.f32(float)
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define float @fabs(float %a) nounwind {
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; RV32I-LABEL: fabs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fabs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: addiw a1, a1, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%1 = call float @llvm.fabs.f32(float %a)
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ret float %1
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}
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