forked from OSchip/llvm-project
Keep track of phi join registers explicitly in LiveVariables.
Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply defined registers. That doesn't work if the phi join is implicitly defined in all but one of the predecessors. llvm-svn: 96994
This commit is contained in:
Jakob Stoklund Olesen
parent
c18086ae17
commit
38b76e27a7
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@ -124,6 +124,11 @@ private:
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///
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std::vector<VarInfo> VirtRegInfo;
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/// PHIJoins - list of virtual registers that are PHI joins. These registers
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/// may have multiple definitions, and they require special handling when
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/// building live intervals.
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SparseBitVector<> PHIJoins;
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/// ReservedRegisters - This vector keeps track of which registers
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/// are reserved register which are not allocatable by the target machine.
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/// We can not track liveness for values that are in this set.
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@ -295,6 +300,12 @@ public:
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void addNewBlock(MachineBasicBlock *BB,
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MachineBasicBlock *DomBB,
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MachineBasicBlock *SuccBB);
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/// isPHIJoin - Return true if Reg is a phi join register.
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bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
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/// setPHIJoin - Mark Reg as a phi join register.
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void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
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};
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} // End llvm namespace
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@ -329,24 +329,43 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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DEBUG(dbgs() << " +" << NewLR);
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interval.addRange(NewLR);
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
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E = vi.AliveBlocks.end(); I != E; ++I) {
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MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
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LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
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interval.addRange(LR);
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DEBUG(dbgs() << " +" << LR);
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bool PHIJoin = lv_->isPHIJoin(interval.reg);
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if (PHIJoin) {
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// A phi join register is killed at the end of the MBB and revived as a new
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// valno in the killing blocks.
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assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
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DEBUG(dbgs() << " phi-join");
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ValNo->addKill(indexes_->getTerminatorGap(mbb));
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ValNo->setHasPHIKill(true);
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} else {
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
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E = vi.AliveBlocks.end(); I != E; ++I) {
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MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
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LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
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interval.addRange(LR);
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DEBUG(dbgs() << " +" << LR);
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}
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}
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// Finally, this virtual register is live from the start of any killing
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// block to the 'use' slot of the killing instruction.
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for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineInstr *Kill = vi.Kills[i];
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SlotIndex killIdx =
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getInstructionIndex(Kill).getDefIndex();
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LiveRange LR(getMBBStartIdx(Kill->getParent()), killIdx, ValNo);
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SlotIndex Start = getMBBStartIdx(Kill->getParent());
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SlotIndex killIdx = getInstructionIndex(Kill).getDefIndex();
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// Create interval with one of a NEW value number. Note that this value
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// number isn't actually defined by an instruction, weird huh? :)
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if (PHIJoin) {
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ValNo = interval.getNextValue(SlotIndex(Start, true), 0, false,
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VNInfoAllocator);
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ValNo->setIsPHIDef(true);
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}
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LiveRange LR(Start, killIdx, ValNo);
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interval.addRange(LR);
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ValNo->addKill(killIdx);
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DEBUG(dbgs() << " +" << LR);
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@ -409,48 +428,11 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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interval.print(dbgs(), tri_);
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});
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} else {
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// Otherwise, this must be because of phi elimination. If this is the
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// first redefinition of the vreg that we have seen, go back and change
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// the live range in the PHI block to be a different value number.
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if (interval.containsOneValue()) {
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VNInfo *VNI = interval.getValNumInfo(0);
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// Phi elimination may have reused the register for multiple identical
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// phi nodes. There will be a kill per phi. Remove the old ranges that
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// we now know have an incorrect number.
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for (unsigned ki=0, ke=vi.Kills.size(); ki != ke; ++ki) {
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MachineInstr *Killer = vi.Kills[ki];
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SlotIndex Start = getMBBStartIdx(Killer->getParent());
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SlotIndex End = getInstructionIndex(Killer).getDefIndex();
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DEBUG({
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dbgs() << "\n\t\trenaming [" << Start << "," << End << "] in: ";
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interval.print(dbgs(), tri_);
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});
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interval.removeRange(Start, End);
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// Replace the interval with one of a NEW value number. Note that
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// this value number isn't actually defined by an instruction, weird
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// huh? :)
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LiveRange LR(Start, End,
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interval.getNextValue(SlotIndex(Start, true),
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0, false, VNInfoAllocator));
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LR.valno->setIsPHIDef(true);
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interval.addRange(LR);
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LR.valno->addKill(End);
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}
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MachineBasicBlock *killMBB = getMBBFromIndex(VNI->def);
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VNI->addKill(indexes_->getTerminatorGap(killMBB));
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VNI->setHasPHIKill(true);
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DEBUG({
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dbgs() << " RESULT: ";
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interval.print(dbgs(), tri_);
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});
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}
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assert(lv_->isPHIJoin(interval.reg) && "Multiply defined register");
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// In the case of PHI elimination, each variable definition is only
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// live until the end of the block. We've already taken care of the
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// rest of the live range.
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SlotIndex defIndex = MIIdx.getDefIndex();
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if (MO.isEarlyClobber())
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defIndex = MIIdx.getUseIndex();
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@ -468,7 +450,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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interval.addRange(LR);
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ValNo->addKill(indexes_->getTerminatorGap(mbb));
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ValNo->setHasPHIKill(true);
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DEBUG(dbgs() << " +" << LR);
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DEBUG(dbgs() << " phi-join +" << LR);
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}
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}
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@ -510,6 +510,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
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std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
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PHIJoins.clear();
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/// Get some space for a respectable number of registers.
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VirtRegInfo.resize(64);
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@ -223,6 +223,7 @@ void llvm::PHIElimination::LowerAtomicPHINode(
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// Increment use count of the newly created virtual register.
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VI.NumUses++;
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LV->setPHIJoin(IncomingReg);
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// When we are reusing the incoming register, it may already have been
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// killed in this block. The old kill will also have been inserted at
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@ -0,0 +1,146 @@
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; RUN: llc < %s
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; PR6363
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;
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; This test case creates a phi join register with a single definition. The other
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; predecessor blocks are implicit-def.
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;
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; If LiveIntervalAnalysis fails to recognize this as a phi join, the coalescer
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; will detect an infinity valno loop.
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;
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define i32 @decode(i8* nocapture %input, i32 %offset, i8* nocapture %output) nounwind {
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entry:
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br i1 undef, label %meshBB86, label %meshBB102
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bb: ; preds = %meshBB106, %meshBB102
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br i1 false, label %bb9, label %meshBB90
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bb.nph: ; preds = %meshBB90
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br label %meshBB114
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bb.nph.fragment: ; preds = %meshBB114
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br label %meshBB118
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bb1.fragment: ; preds = %meshBB118
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br i1 false, label %bb2, label %bb3
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bb2: ; preds = %bb1.fragment
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br label %meshBB74
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bb2.fragment15: ; preds = %meshBB74
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br label %meshBB98
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bb3: ; preds = %bb1.fragment
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br i1 undef, label %meshBB, label %meshBB102
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bb4: ; preds = %meshBB
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br label %meshBB118
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bb4.fragment: ; preds = %meshBB118
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br label %meshBB82
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bb5: ; preds = %meshBB102, %meshBB82
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br i1 false, label %bb6, label %bb7
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bb6: ; preds = %bb5
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br label %bb7
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bb7: ; preds = %meshBB98, %bb6, %bb5
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br label %meshBB114
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bb7.fragment: ; preds = %meshBB114
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br i1 undef, label %meshBB74, label %bb9
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bb9: ; preds = %bb7.fragment, %bb
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br label %bb1.i23
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bb1.i23: ; preds = %meshBB110, %bb9
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br i1 undef, label %meshBB106, label %meshBB110
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skip_to_newline.exit26: ; preds = %meshBB106
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br label %meshBB86
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skip_to_newline.exit26.fragment: ; preds = %meshBB86
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br i1 false, label %meshBB90, label %meshBB106
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bb11.fragment: ; preds = %meshBB90, %meshBB86
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br label %meshBB122
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bb1.i: ; preds = %meshBB122, %meshBB
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%ooffset.2.lcssa.phi.SV.phi203 = phi i32 [ 0, %meshBB122 ], [ %ooffset.2.lcssa.phi.SV.phi233, %meshBB ] ; <i32> [#uses=1]
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br label %meshBB98
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bb1.i.fragment: ; preds = %meshBB98
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br i1 undef, label %meshBB78, label %meshBB
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skip_to_newline.exit: ; preds = %meshBB78
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br i1 undef, label %bb12, label %meshBB110
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bb12: ; preds = %skip_to_newline.exit
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br label %meshBB94
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bb12.fragment: ; preds = %meshBB94
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br i1 false, label %bb13, label %meshBB78
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bb13: ; preds = %bb12.fragment
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br label %meshBB82
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bb13.fragment: ; preds = %meshBB82
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br i1 undef, label %meshBB94, label %meshBB122
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bb14: ; preds = %meshBB94
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ret i32 %ooffset.2.lcssa.phi.SV.phi250
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bb15: ; preds = %meshBB122, %meshBB110, %meshBB78
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unreachable
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meshBB: ; preds = %bb1.i.fragment, %bb3
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%ooffset.2.lcssa.phi.SV.phi233 = phi i32 [ undef, %bb3 ], [ %ooffset.2.lcssa.phi.SV.phi209, %bb1.i.fragment ] ; <i32> [#uses=1]
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br i1 undef, label %bb1.i, label %bb4
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meshBB74: ; preds = %bb7.fragment, %bb2
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br i1 false, label %meshBB118, label %bb2.fragment15
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meshBB78: ; preds = %bb12.fragment, %bb1.i.fragment
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%ooffset.2.lcssa.phi.SV.phi239 = phi i32 [ %ooffset.2.lcssa.phi.SV.phi209, %bb1.i.fragment ], [ %ooffset.2.lcssa.phi.SV.phi250, %bb12.fragment ] ; <i32> [#uses=1]
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br i1 false, label %bb15, label %skip_to_newline.exit
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meshBB82: ; preds = %bb13, %bb4.fragment
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br i1 false, label %bb5, label %bb13.fragment
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meshBB86: ; preds = %skip_to_newline.exit26, %entry
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br i1 undef, label %skip_to_newline.exit26.fragment, label %bb11.fragment
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meshBB90: ; preds = %skip_to_newline.exit26.fragment, %bb
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br i1 false, label %bb11.fragment, label %bb.nph
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meshBB94: ; preds = %bb13.fragment, %bb12
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%ooffset.2.lcssa.phi.SV.phi250 = phi i32 [ 0, %bb13.fragment ], [ %ooffset.2.lcssa.phi.SV.phi239, %bb12 ] ; <i32> [#uses=2]
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br i1 false, label %bb12.fragment, label %bb14
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meshBB98: ; preds = %bb1.i, %bb2.fragment15
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%ooffset.2.lcssa.phi.SV.phi209 = phi i32 [ undef, %bb2.fragment15 ], [ %ooffset.2.lcssa.phi.SV.phi203, %bb1.i ] ; <i32> [#uses=2]
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br i1 undef, label %bb1.i.fragment, label %bb7
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meshBB102: ; preds = %bb3, %entry
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br i1 undef, label %bb5, label %bb
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meshBB106: ; preds = %skip_to_newline.exit26.fragment, %bb1.i23
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br i1 undef, label %bb, label %skip_to_newline.exit26
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meshBB110: ; preds = %skip_to_newline.exit, %bb1.i23
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br i1 false, label %bb15, label %bb1.i23
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meshBB114: ; preds = %bb7, %bb.nph
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%meshStackVariable115.phi = phi i32 [ 19, %bb7 ], [ 8, %bb.nph ] ; <i32> [#uses=0]
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br i1 undef, label %bb.nph.fragment, label %bb7.fragment
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meshBB118: ; preds = %meshBB74, %bb4, %bb.nph.fragment
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%meshCmp121 = icmp eq i32 undef, 10 ; <i1> [#uses=1]
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br i1 %meshCmp121, label %bb4.fragment, label %bb1.fragment
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meshBB122: ; preds = %bb13.fragment, %bb11.fragment
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br i1 false, label %bb1.i, label %bb15
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}
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