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Trivial cleanups. 

This just clang formats and cleans comments in an area I am about to
post a patch for review.

llvm-svn: 269946
This commit is contained in:
Rafael Espindola 2016-05-18 16:00:24 +00:00
parent 891fccc0c1
commit 38af4d6347
13 changed files with 35 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
llvm/include/llvm/CodeGen/CommandFlags.h
View File

@ -46,20 +46,18 @@ MAttrs("mattr",
cl::desc("Target specific attributes (-mattr=help for details)"),
cl::value_desc("a1,+a2,-a3,..."));
cl::opt<Reloc::Model>
RelocModel("relocation-model",
cl::desc("Choose relocation model"),
cl::init(Reloc::Default),
cl::values(
clEnumValN(Reloc::Default, "default",
"Target default relocation model"),
clEnumValN(Reloc::Static, "static",
"Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
cl::opt<Reloc::Model> RelocModel(
"relocation-model", cl::desc("Choose relocation model"),
cl::init(Reloc::Default),
cl::values(
clEnumValN(Reloc::Default, "default",
"Target default relocation model"),
clEnumValN(Reloc::Static, "static", "Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
cl::opt<ThreadModel::Model>
TMModel("thread-model",

2
llvm/include/llvm/Support/CodeGen.h
View File

@ -19,7 +19,7 @@ namespace llvm {
// Relocation model types.
namespace Reloc {
enum Model { Default, Static, PIC_, DynamicNoPIC };
enum Model { Default, Static, PIC_, DynamicNoPIC };
}
// Code model types.

2
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -161,7 +161,7 @@ static void initReciprocals(AArch64TargetMachine& TM, AArch64Subtarget& ST)
TM.Options.Reciprocals.setDefaults("vec-divd", false, ExtraStepsD);
}
/// TargetMachine ctor - Create an AArch64 architecture model.
/// Create an AArch64 architecture model.
///
AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,

4
llvm/lib/Target/AArch64/AArch64TargetMachine.h
View File

@ -49,7 +49,7 @@ private:
AArch64Subtarget Subtarget;
};
// AArch64leTargetMachine - AArch64 little endian target machine.
// AArch64 little endian target machine.
//
class AArch64leTargetMachine : public AArch64TargetMachine {
virtual void anchor();
@ -60,7 +60,7 @@ public:
CodeGenOpt::Level OL);
};
// AArch64beTargetMachine - AArch64 big endian target machine.
// AArch64 big endian target machine.
//
class AArch64beTargetMachine : public AArch64TargetMachine {
virtual void anchor();

2
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -172,7 +172,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
return Ret;
}
/// TargetMachine ctor - Create an ARM architecture model.
/// Create an ARM architecture model.
///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,

12
llvm/lib/Target/ARM/ARMTargetMachine.h
View File

@ -58,7 +58,7 @@ public:
}
};
/// ARMTargetMachine - ARM target machine.
/// ARM target machine.
///
class ARMTargetMachine : public ARMBaseTargetMachine {
virtual void anchor();
@ -68,7 +68,7 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
};
/// ARMLETargetMachine - ARM little endian target machine.
/// ARM little endian target machine.
///
class ARMLETargetMachine : public ARMTargetMachine {
void anchor() override;
@ -79,7 +79,7 @@ public:
CodeGenOpt::Level OL);
};
/// ARMBETargetMachine - ARM big endian target machine.
/// ARM big endian target machine.
///
class ARMBETargetMachine : public ARMTargetMachine {
void anchor() override;
@ -90,7 +90,7 @@ public:
CodeGenOpt::Level OL);
};
/// ThumbTargetMachine - Thumb target machine.
/// Thumb target machine.
/// Due to the way architectures are handled, this represents both
/// Thumb-1 and Thumb-2.
///
@ -103,7 +103,7 @@ public:
bool isLittle);
};
/// ThumbLETargetMachine - Thumb little endian target machine.
/// Thumb little endian target machine.
///
class ThumbLETargetMachine : public ThumbTargetMachine {
void anchor() override;
@ -114,7 +114,7 @@ public:
CodeGenOpt::Level OL);
};
/// ThumbBETargetMachine - Thumb big endian target machine.
/// Thumb big endian target machine.
///
class ThumbBETargetMachine : public ThumbTargetMachine {
void anchor() override;

4
llvm/lib/Target/Mips/MipsTargetMachine.h
View File

@ -68,7 +68,7 @@ public:
const MipsABIInfo &getABI() const { return ABI; }
};
/// MipsebTargetMachine - Mips32/64 big endian target machine.
/// Mips32/64 big endian target machine.
///
class MipsebTargetMachine : public MipsTargetMachine {
virtual void anchor();
@ -79,7 +79,7 @@ public:
CodeGenOpt::Level OL);
};
/// MipselTargetMachine - Mips32/64 little endian target machine.
/// Mips32/64 little endian target machine.
///
class MipselTargetMachine : public MipsTargetMachine {
virtual void anchor();

6
llvm/lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -21,7 +21,7 @@
namespace llvm {
/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
/// Common code between 32-bit and 64-bit PowerPC targets.
///
class PPCTargetMachine : public LLVMTargetMachine {
public:
@ -57,7 +57,7 @@ public:
};
};
/// PPC32TargetMachine - PowerPC 32-bit target machine.
/// PowerPC 32-bit target machine.
///
class PPC32TargetMachine : public PPCTargetMachine {
virtual void anchor();
@ -68,7 +68,7 @@ public:
CodeGenOpt::Level OL);
};
/// PPC64TargetMachine - PowerPC 64-bit target machine.
/// PowerPC 64-bit target machine.
///
class PPC64TargetMachine : public PPCTargetMachine {
virtual void anchor();

2
llvm/lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -53,7 +53,7 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) {
return Ret;
}
/// SparcTargetMachine ctor - Create an ILP32 architecture model
/// Create an ILP32 architecture model
///
SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,

4
llvm/lib/Target/Sparc/SparcTargetMachine.h
View File

@ -40,7 +40,7 @@ public:
}
};
/// SparcV8TargetMachine - Sparc 32-bit target machine
/// Sparc 32-bit target machine
///
class SparcV8TargetMachine : public SparcTargetMachine {
virtual void anchor();
@ -51,7 +51,7 @@ public:
CodeGenOpt::Level OL);
};
/// SparcV9TargetMachine - Sparc 64-bit target machine
/// Sparc 64-bit target machine
///
class SparcV9TargetMachine : public SparcTargetMachine {
virtual void anchor();

4
llvm/lib/Target/TargetMachine.cpp
View File

@ -71,8 +71,8 @@ void TargetMachine::resetTargetOptions(const Function &F) const {
RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math");
}
/// getRelocationModel - Returns the code generation relocation model. The
/// choices are static, PIC, and dynamic-no-pic, and target default.
/// Returns the code generation relocation model. The choices are static, PIC,
/// and dynamic-no-pic, and target default.
Reloc::Model TargetMachine::getRelocationModel() const {
if (!CodeGenInfo)
return Reloc::Default;

2
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -106,7 +106,7 @@ static std::string computeDataLayout(const Triple &TT) {
return Ret;
}
/// X86TargetMachine ctor - Create an X86 target.
/// Create an X86 target.
///
X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,

2
llvm/lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -21,7 +21,7 @@
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
/// XCoreTargetMachine ctor - Create an ILP32 architecture model
/// Create an ILP32 architecture model
///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,