From 387ce30685ae178c87588fe9b5e18d7f1ff76864 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Wed, 29 Apr 2015 17:23:22 +0000 Subject: [PATCH] [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions Differential Revision: http://reviews.llvm.org/D8894 llvm-svn: 236131 --- llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 12 ++++++++++++ llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 10 +++++----- llvm/test/MC/Disassembler/Mips/micromips32r6.txt | 8 ++++++++ llvm/test/MC/Mips/micromips32r6/valid.s | 4 ++++ 4 files changed, 29 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index a0f5dd84cdf0..59cf3e79d137 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -23,6 +23,10 @@ class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>; +class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>; +class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>; +class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>; +class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>; class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>; class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>; @@ -36,6 +40,10 @@ class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>; class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>; class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>; class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>; +class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>; +class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>; +class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>; +class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>; class BC_MMR6_DESC_BASE : BRANCH_DESC_BASE, MMR6Arch { @@ -90,6 +98,10 @@ def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC, ISA_MICROMIPS32R6; def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6; +def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6; +def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6; +def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6; +def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6; def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6; def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6; def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6; diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index e80d9f44772c..62c55144779c 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -453,7 +453,7 @@ class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> { } class MUL_R6_DESC_BASE { + SDPatternOperator Op=null_frag> : MipsR6Arch { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); @@ -709,10 +709,10 @@ def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6; def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6; def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6; def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6; -def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6; -def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; -def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; -def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; +def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6; +def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; +def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; +def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; def NAL; // BAL with rd=0 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt index 36bbce2d8201..6e2990ccbcbb 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt @@ -18,6 +18,14 @@ # CHECK: cache 1, 8($5) 0x20 0x25 0x60 0x08 +0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5 + +0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5 + +0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5 + +0x00 0xa4,0x18,0xd8 # CHECK: muhu $3, $4, $5 + # CHECK: pref 1, 8($5) 0x60 0x25 0x20 0x08 diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index e1c2edfa1326..253f08e22018 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -8,6 +8,10 @@ bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] + mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] + muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] + mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] + muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08] sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90] subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]