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Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 

rdar://problem/9224276

llvm-svn: 128749
This commit is contained in:
Johnny Chen 2011-04-01 23:30:25 +00:00
parent 6615fa1de0
commit 387b36eaae
2 changed files with 14 additions and 0 deletions
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1
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -1983,6 +1983,7 @@ def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
bits<4> Rd;
bits<4> Rm;
let Inst{19-16} = 0b0000;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{3-0} = Rm;

13
llvm/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt Normal file
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@ -0,0 +1,13 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=0 Name=PHI Format=(42)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
# The instruction is UNPREDICTABLE, and is not a valid intruction.
#
# See also
# A8.6.97 MOV (register)
0x2 0xd0 0xbc 0xf1