forked from OSchip/llvm-project
[VE] Support shift operation instructions in MC layer
Summary: Add regression tests of asmparser, mccodeemitter, and disassembler for shift operation instructions. Also change asmparser to support UImm7 operand. And, add new SLD/SRD/SLA instructions also. Differential Revision: https://reviews.llvm.org/D81324
This commit is contained in:
Kazushi (Jam) Marukawa
Simon Moll
parent
772349de88
commit
385adc4720
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@ -191,6 +191,17 @@ public:
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bool isMEMri() const { return Kind == k_MemoryRegImm; }
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bool isMEMzi() const { return Kind == k_MemoryZeroImm; }
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bool isCCOp() const { return Kind == k_CCOp; }
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bool isUImm7() {
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if (!isImm())
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return false;
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// Constant case
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if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
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int64_t Value = ConstExpr->getValue();
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return isUInt<7>(Value);
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}
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return false;
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}
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bool isSImm7() {
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if (!isImm())
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return false;
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@ -340,6 +351,10 @@ public:
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addExpr(Inst, Expr);
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}
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void addUImm7Operands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addSImm7Operands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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@ -39,6 +39,10 @@ include "VEInstrFormats.td"
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// e.g. 0.0 (0x00000000) or -2.0 (0xC0000000=(2)1).
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//===----------------------------------------------------------------------===//
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def ULO7 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() & 0x7f,
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SDLoc(N), MVT::i32);
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}]>;
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def LO7 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
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SDLoc(N), MVT::i32);
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@ -117,8 +121,13 @@ def uimm6 : Operand<i32>, PatLeaf<(imm), [{
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return isUInt<6>(N->getZExtValue()); }]>;
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// uimm7 - Generic immediate value.
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def UImm7AsmOperand : AsmOperandClass {
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let Name = "UImm7";
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}
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def uimm7 : Operand<i32>, PatLeaf<(imm), [{
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return isUInt<7>(N->getZExtValue()); }]>;
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return isUInt<7>(N->getZExtValue()); }], ULO7> {
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let ParserMatchClass = UImm7AsmOperand;
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}
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// simm7 - Generic immediate value.
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def SImm7AsmOperand : AsmOperandClass {
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@ -493,6 +502,44 @@ multiclass RRIm<string opcStr, bits<8>opc,
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[(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>;
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}
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// Special RR multiclass for 128 bits shift left instruction.
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// e.g. SLD
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let Constraints = "$hi = $sx", DisableEncoding = "$hi", hasSideEffects = 0 in
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multiclass RRILDm<string opcStr, bits<8>opc,
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RegisterClass RC, ValueType Ty,
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SDPatternOperator OpNode = null_frag> {
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def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cz = 0 in
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def rmr : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cy = 0 in
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def rri : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, uimm7:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cy = 0, cz = 0 in
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def rmi : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, uimm7:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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}
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// Special RR multiclass for 128 bits shift right instruction.
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// e.g. SRD
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let Constraints = "$low = $sx", DisableEncoding = "$low", hasSideEffects = 0 in
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multiclass RRIRDm<string opcStr, bits<8>opc,
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RegisterClass RC, ValueType Ty,
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SDPatternOperator OpNode = null_frag> {
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def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cz = 0 in
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def mrr : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cy = 0 in
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def rri : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, uimm7:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cy = 0, cz = 0 in
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def mri : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, uimm7:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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}
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// Generic RR multiclass with an argument.
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// e.g. LDZ, PCNT, and BRV
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let cy = 0, sy = 0, hasSideEffects = 0 in
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@ -947,17 +994,20 @@ def : MnemonicAlias<"cmov.s", "cmov.s.at">;
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defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
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// Section 8.6.2 - SLD (Shift Left Double)
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defm SLD : RRILDm<"sld", 0x64, I64, i64>;
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// Section 8.6.3 - SRL (Shift Right Logical)
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defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
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// Section 8.6.4 - SRD (Shift Right Double)
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defm SRD : RRIRDm<"srd", 0x74, I64, i64>;
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// Section 8.6.5 - SLA (Shift Left Arithmetic)
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defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
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let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
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// Section 8.6.6 - SLAX (Shift Left Arithmetic)
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defm SLAL : RRIm<"sla.l", 0x57, I64, i64>;
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// Section 8.6.7 - SRA (Shift Right Arithmetic)
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defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: sla.w.sx %s11, %s11, %s11
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x66]
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sla.w.sx %s11, %s11, %s11
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# CHECK-INST: sla.w.zx %s11, %s11, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x8b,0x66]
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sla.w.zx %s11, %s11, 63
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# CHECK-INST: sla.l %s11, %s11, 127
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x57]
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sla.l %s11, %s11, 127
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# CHECK-INST: sla.w.sx %s11, %s11, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x66]
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sla.w.sx %s11, %s11, 64
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# CHECK-INST: sla.w.zx %s11, (32)1, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x8b,0x66]
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sla.w.zx %s11, (32)1, 64
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# CHECK-INST: sla.l %s11, (32)0, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x57]
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sla.l %s11, (32)0, 63
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: sld %s11, %s11, %s11
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x64]
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sld %s11, %s11, %s11
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# CHECK-INST: sld %s11, %s11, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x64]
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sld %s11, %s11, 63
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# CHECK-INST: sld %s11, %s11, 127
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x64]
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sld %s11, %s11, 127
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# CHECK-INST: sld %s11, %s11, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x64]
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sld %s11, %s11, 64
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# CHECK-INST: sld %s11, (32)1, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x64]
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sld %s11, (32)1, 64
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# CHECK-INST: sld %s11, (32)0, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x64]
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sld %s11, (32)0, 63
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: sll %s11, %s11, %s11
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x65]
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sll %s11, %s11, %s11
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# CHECK-INST: sll %s11, %s11, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x65]
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sll %s11, %s11, 63
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# CHECK-INST: sll %s11, %s11, 127
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x65]
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sll %s11, %s11, 127
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# CHECK-INST: sll %s11, %s11, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x65]
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sll %s11, %s11, 64
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# CHECK-INST: sll %s11, (32)1, 35
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x23,0x0b,0x65]
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sll %s11, (32)1, 35
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# CHECK-INST: sll %s11, (32)0, 23
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x17,0x0b,0x65]
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sll %s11, (32)0, 23
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: sra.w.sx %s11, %s11, %s11
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x76]
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sra.w.sx %s11, %s11, %s11
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# CHECK-INST: sra.w.zx %s11, %s11, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x8b,0x76]
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sra.w.zx %s11, %s11, 63
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# CHECK-INST: sra.l %s11, %s11, 127
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x77]
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sra.l %s11, %s11, 127
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# CHECK-INST: sra.w.sx %s11, %s11, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x76]
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sra.w.sx %s11, %s11, 64
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# CHECK-INST: sra.w.zx %s11, (32)1, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x8b,0x76]
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sra.w.zx %s11, (32)1, 64
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# CHECK-INST: sra.l %s11, (32)0, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x77]
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sra.l %s11, (32)0, 63
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: srd %s11, %s11, %s11
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x74]
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srd %s11, %s11, %s11
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# CHECK-INST: srd %s11, %s11, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x74]
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srd %s11, %s11, 63
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# CHECK-INST: srd %s11, %s11, 127
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x74]
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srd %s11, %s11, 127
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# CHECK-INST: srd %s11, %s11, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x74]
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srd %s11, %s11, 64
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# CHECK-INST: srd %s11, (32)1, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x74]
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srd %s11, (32)1, 64
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# CHECK-INST: srd %s11, (32)0, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x74]
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srd %s11, (32)0, 63
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: srl %s11, %s11, %s11
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x75]
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srl %s11, %s11, %s11
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# CHECK-INST: srl %s11, %s11, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x75]
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srl %s11, %s11, 63
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# CHECK-INST: srl %s11, %s11, 127
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x75]
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srl %s11, %s11, 127
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# CHECK-INST: srl %s11, %s11, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x75]
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srl %s11, %s11, 64
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# CHECK-INST: srl %s11, (32)1, 64
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x75]
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srl %s11, (32)1, 64
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# CHECK-INST: srl %s11, (32)0, 63
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x75]
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srl %s11, (32)0, 63
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