forked from OSchip/llvm-project
Cleanup the scalar FMA3 definitions. Add patterns to fold loads with scalar forms.
llvm-svn: 162260
This commit is contained in:
Craig Topper
parent
28a26c8d99
commit
384fae2f0d
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@ -245,23 +245,27 @@ let Predicates = [HasFMA] in {
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let Constraints = "$src1 = $dst" in {
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multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
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RegisterClass RC> {
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let neverHasSideEffects = 1 in {
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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} // neverHasSideEffects = 1
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RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
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SDPatternOperator OpNode = null_frag, bit MayLoad = 1> {
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
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let mayLoad = MayLoad in
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def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1,
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(mem_frag addr:$src3))))]>;
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}
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multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
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ComplexPattern mem_cpat, Intrinsic IntId,
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RegisterClass RC, SDNode OpNode, ValueType OpVT> {
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RegisterClass RC> {
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def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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@ -274,44 +278,45 @@ multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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}
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} // Constraints = "$src1 = $dst"
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multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, Intrinsic IntF32, Intrinsic IntF64,
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SDNode OpNode> {
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defm SSr132 : fma3s_rm<opc132, !strconcat(OpStr, "132ss"), f32mem, FR32>;
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defm SSr231 : fma3s_rm<opc231, !strconcat(OpStr, "231ss"), f32mem, FR32>;
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defm SDr132 : fma3s_rm<opc132, !strconcat(OpStr, "132sd"), f64mem, FR64>,
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VEX_W;
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defm SDr231 : fma3s_rm<opc231, !strconcat(OpStr, "231sd"), f64mem, FR64>,
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VEX_W;
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defm SSr213 : fma3s_rm_int <opc213, !strconcat(OpStr, "213ss"), ssmem,
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sse_load_f32, IntF32, FR32, OpNode, f32>;
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defm SDr213 : fma3s_rm_int <opc213, !strconcat(OpStr, "213sd"), sdmem,
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sse_load_f64, IntF64, FR64, OpNode, f64>, VEX_W;
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string OpStr, string PackTy, Intrinsic Int,
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SDNode OpNode, RegisterClass RC, ValueType OpVT,
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X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
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ComplexPattern mem_cpat> {
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let neverHasSideEffects = 1 in {
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defm r132 : fma3s_rm<opc132, !strconcat(OpStr, !strconcat("132", PackTy)),
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x86memop, RC, OpVT, mem_frag>;
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defm r231 : fma3s_rm<opc231, !strconcat(OpStr, !strconcat("231", PackTy)),
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x86memop, RC, OpVT, mem_frag>;
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}
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defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
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int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
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defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
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int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
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defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
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x86memop, RC, OpVT, mem_frag, OpNode, 0>,
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fma3s_rm_int<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
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memop, mem_cpat, Int, RC>;
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}
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defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
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int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
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defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
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int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
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multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, Intrinsic IntF32, Intrinsic IntF64,
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SDNode OpNode> {
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defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", IntF32, OpNode,
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FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
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defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", IntF64, OpNode,
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FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
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}
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defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
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int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
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defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
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int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
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defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
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int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
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defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
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int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
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//===----------------------------------------------------------------------===//
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