maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[GlobalISel] Relax vector G_SELECT assertion. 

For vector operands, the `select` instruction supports both vector and
non-vector conditions.  The MIR builder had an overly restrictive
assertion, that only accepted vector conditions for vector selects
(in effect implementing ISD::VSELECT).

Make it possible to express the full range of G_SELECTs.

llvm-svn: 297207
This commit is contained in:
Ahmed Bougacha 2017-03-07 20:53:03 +00:00
parent 70dd6c2212
commit 38455ea8a6
2 changed files with 15 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
View File

@ -568,9 +568,10 @@ MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
if (ResTy.isScalar() || ResTy.isPointer())
assert(MRI->getType(Tst).isScalar() && "type mismatch");
else
assert(MRI->getType(Tst).isVector() &&
assert((MRI->getType(Tst).isScalar() ||
(MRI->getType(Tst).isVector() &&
MRI->getType(Tst).getNumElements() ==
MRI->getType(Op0).getNumElements() &&
MRI->getType(Op0).getNumElements())) &&
"type mismatch");
#endif

11
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View File

@ -945,6 +945,17 @@ define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) {
ret i8* %res
}
; CHECK-LABEL: name: test_select_vec
; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0
; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q0
; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q1
; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
; CHECK: %q0 = COPY [[RES]]
define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
%res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs
ret <4 x i32> %res
}
; CHECK-LABEL: name: test_vselect_vec
; CHECK: [[TST32:%[0-9]+]](<4 x s32>) = COPY %q0
; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q1