forked from OSchip/llvm-project
[GlobalISel][TableGen] Fix handling of default operands
When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
This commit is contained in:
Diana Picus
parent
859d302349
commit
382602f176
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@ -387,6 +387,42 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
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def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
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[(set GPR32:$dst, (xor GPR32:$src1, -4))]>;
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//===- Test a simple pattern with multiple operands with defaults. --------===//
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//
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// CHECK-LABEL: if ([&]() {
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// CHECK-NEXT: MachineInstr &MI0 = I;
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// CHECK-NEXT: if (MI0.getNumOperands() < 3)
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// CHECK-NEXT: return false;
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// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_XOR) &&
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// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: (isOperandImmEqual(MI0.getOperand(2), -5, MRI))))) {
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// CHECK-NEXT: // (xor:i32 GPR32:i32:$src1, -5:i32) => (XORManyDefaults:i32 GPR32:i32:$src1)
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// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORManyDefaults));
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// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/);
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// CHECK-NEXT: MIB.addImm(-1);
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// CHECK-NEXT: MIB.addReg(MyTarget::R0);
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// CHECK-NEXT: MIB.addReg(MyTarget::R0);
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// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src1*/);
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// CHECK-NEXT: for (const auto *FromMI : {&MI0, })
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// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
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// CHECK-NEXT: MIB.addMemOperand(MMO);
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// CHECK-NEXT: I.eraseFromParent();
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// CHECK-NEXT: MachineInstr &NewI = *MIB;
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// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
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// CHECK-NEXT: return true;
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// CHECK-NEXT: }
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// CHECK-NEXT: return false;
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// CHECK-NEXT: }()) { return true; }
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// The -5 is just to distinguish it from the other cases.
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def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1),
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[(set GPR32:$dst, (xor GPR32:$src1, -5))]>;
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//===- Test a simple pattern with constant immediate operands. ------------===//
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//
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// This must precede the 3-register variants because constant immediates have
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@ -1242,6 +1242,8 @@ private:
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Error importExplicitUseRenderer(BuildMIAction &DstMIBuilder,
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TreePatternNode *DstChild,
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const InstructionMatcher &InsnMatcher) const;
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Error importDefaultOperandRenderers(BuildMIAction &DstMIBuilder,
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DagInit *DefaultOps) const;
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Error
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importImplicitDefRenderers(BuildMIAction &DstMIBuilder,
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const std::vector<Record *> &ImplicitDefs) const;
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@ -1509,59 +1511,23 @@ Expected<BuildMIAction &> GlobalISelEmitter::createAndImportInstructionRenderer(
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DstMIBuilder.addRenderer<CopyRenderer>(InsnMatcher, DstIOperand.Name);
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}
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// Figure out which operands need defaults inserted. Operands that subclass
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// OperandWithDefaultOps are considered from left to right until we have
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// enough operands to render the instruction.
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SmallSet<unsigned, 2> DefaultOperands;
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unsigned DstINumUses = DstI.Operands.size() - DstI.Operands.NumDefs;
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unsigned NumDefaultOperands = 0;
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for (unsigned I = 0; I < DstINumUses &&
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DstINumUses > Dst->getNumChildren() + NumDefaultOperands;
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++I) {
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const auto &DstIOperand = DstI.Operands[DstI.Operands.NumDefs + I];
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if (DstIOperand.Rec->isSubClassOf("OperandWithDefaultOps")) {
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DefaultOperands.insert(I);
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NumDefaultOperands +=
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DstIOperand.Rec->getValueAsDag("DefaultOps")->getNumArgs();
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}
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}
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if (DstINumUses > Dst->getNumChildren() + DefaultOperands.size())
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return failedImport("Insufficient operands supplied and default ops "
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"couldn't make up the shortfall");
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if (DstINumUses < Dst->getNumChildren() + DefaultOperands.size())
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return failedImport("Too many operands supplied");
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// Render the explicit uses.
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unsigned Child = 0;
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unsigned DstINumUses = DstI.Operands.size() - DstI.Operands.NumDefs;
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unsigned NumDefaultOps = 0;
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for (unsigned I = 0; I != DstINumUses; ++I) {
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// If we need to insert default ops here, then do so.
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if (DefaultOperands.count(I)) {
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const auto &DstIOperand = DstI.Operands[DstI.Operands.NumDefs + I];
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const auto &DstIOperand = DstI.Operands[DstI.Operands.NumDefs + I];
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// If the operand has default values, introduce them now.
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// FIXME: Until we have a decent test case that dictates we should do
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// otherwise, we're going to assume that operands with default values cannot
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// be specified in the patterns. Therefore, adding them will not cause us to
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// end up with too many rendered operands.
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if (DstIOperand.Rec->isSubClassOf("OperandWithDefaultOps")) {
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DagInit *DefaultOps = DstIOperand.Rec->getValueAsDag("DefaultOps");
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for (const auto *DefaultOp : DefaultOps->args()) {
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// Look through ValueType operators.
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if (const DagInit *DefaultDagOp = dyn_cast<DagInit>(DefaultOp)) {
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if (const DefInit *DefaultDagOperator =
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dyn_cast<DefInit>(DefaultDagOp->getOperator())) {
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if (DefaultDagOperator->getDef()->isSubClassOf("ValueType"))
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DefaultOp = DefaultDagOp->getArg(0);
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}
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}
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if (const DefInit *DefaultDefOp = dyn_cast<DefInit>(DefaultOp)) {
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DstMIBuilder.addRenderer<AddRegisterRenderer>(DefaultDefOp->getDef());
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continue;
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}
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if (const IntInit *DefaultIntOp = dyn_cast<IntInit>(DefaultOp)) {
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DstMIBuilder.addRenderer<ImmRenderer>(DefaultIntOp->getValue());
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continue;
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}
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return failedImport("Could not add default op");
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}
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if (auto Error = importDefaultOperandRenderers(DstMIBuilder, DefaultOps))
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return std::move(Error);
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++NumDefaultOps;
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continue;
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}
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@ -1571,9 +1537,44 @@ Expected<BuildMIAction &> GlobalISelEmitter::createAndImportInstructionRenderer(
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++Child;
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}
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if (NumDefaultOps + Dst->getNumChildren() != DstINumUses)
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return failedImport("Expected " + std::to_string(DstINumUses) +
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" used operands but found " +
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std::to_string(Dst->getNumChildren()) +
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" explicit ones and " + std::to_string(NumDefaultOps) +
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" default ones");
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return DstMIBuilder;
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}
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Error GlobalISelEmitter::importDefaultOperandRenderers(
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BuildMIAction &DstMIBuilder, DagInit *DefaultOps) const {
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for (const auto *DefaultOp : DefaultOps->args()) {
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// Look through ValueType operators.
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if (const DagInit *DefaultDagOp = dyn_cast<DagInit>(DefaultOp)) {
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if (const DefInit *DefaultDagOperator =
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dyn_cast<DefInit>(DefaultDagOp->getOperator())) {
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if (DefaultDagOperator->getDef()->isSubClassOf("ValueType"))
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DefaultOp = DefaultDagOp->getArg(0);
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}
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}
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if (const DefInit *DefaultDefOp = dyn_cast<DefInit>(DefaultOp)) {
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DstMIBuilder.addRenderer<AddRegisterRenderer>(DefaultDefOp->getDef());
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continue;
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}
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if (const IntInit *DefaultIntOp = dyn_cast<IntInit>(DefaultOp)) {
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DstMIBuilder.addRenderer<ImmRenderer>(DefaultIntOp->getValue());
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continue;
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}
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return failedImport("Could not add default op");
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}
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return Error::success();
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}
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Error GlobalISelEmitter::importImplicitDefRenderers(
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BuildMIAction &DstMIBuilder,
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const std::vector<Record *> &ImplicitDefs) const {
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