forked from OSchip/llvm-project
[machinesink] fix debug invariance issue
Do not include debug instructions when comparing block sizes with thresholds. Differential Revision: https://reviews.llvm.org/D127208
This commit is contained in:
Markus Lavin
parent
ca4af13e48
commit
3815ae29b5
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@ -246,6 +246,7 @@ public:
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MachineInstrBundleIterator<const MachineInstr, true>;
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MachineInstrBundleIterator<const MachineInstr, true>;
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unsigned size() const { return (unsigned)Insts.size(); }
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unsigned size() const { return (unsigned)Insts.size(); }
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bool sizeWithoutDebugLargerThan(unsigned Limit) const;
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bool empty() const { return Insts.empty(); }
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bool empty() const { return Insts.empty(); }
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MachineInstr &instr_front() { return Insts.front(); }
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MachineInstr &instr_front() { return Insts.front(); }
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@ -1617,6 +1617,16 @@ MachineBasicBlock::liveout_iterator MachineBasicBlock::liveout_begin() const {
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return liveout_iterator(*this, ExceptionPointer, ExceptionSelector, false);
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return liveout_iterator(*this, ExceptionPointer, ExceptionSelector, false);
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}
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}
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bool MachineBasicBlock::sizeWithoutDebugLargerThan(unsigned Limit) const {
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unsigned Cntr = 0;
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auto R = instructionsWithoutDebug(begin(), end());
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for (auto I = R.begin(), E = R.end(); I != E; ++I) {
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if (++Cntr > Limit)
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return true;
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}
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return false;
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}
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const MBBSectionID MBBSectionID::ColdSectionID(MBBSectionID::SectionType::Cold);
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const MBBSectionID MBBSectionID::ColdSectionID(MBBSectionID::SectionType::Cold);
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const MBBSectionID
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const MBBSectionID
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MBBSectionID::ExceptionSectionID(MBBSectionID::SectionType::Exception);
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MBBSectionID::ExceptionSectionID(MBBSectionID::SectionType::Exception);
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@ -1177,7 +1177,7 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock *From,
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// If this BB is too big or the block number in straight line between From
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// If this BB is too big or the block number in straight line between From
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// and To is too big, stop searching to save compiling time.
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// and To is too big, stop searching to save compiling time.
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if (BB->size() > SinkLoadInstsPerBlockThreshold ||
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if (BB->sizeWithoutDebugLargerThan(SinkLoadInstsPerBlockThreshold) ||
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HandledDomBlocks.size() > SinkLoadBlocksThreshold) {
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HandledDomBlocks.size() > SinkLoadBlocksThreshold) {
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for (auto *DomBB : HandledDomBlocks) {
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for (auto *DomBB : HandledDomBlocks) {
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if (DomBB != BB && DT->dominates(DomBB, BB))
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if (DomBB != BB && DT->dominates(DomBB, BB))
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@ -1279,7 +1279,7 @@ bool MachineSinking::SinkIntoCycle(MachineCycle *Cycle, MachineInstr &I) {
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dbgs() << "CycleSink: Not sinking, sink block is the preheader\n");
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dbgs() << "CycleSink: Not sinking, sink block is the preheader\n");
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return false;
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return false;
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}
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}
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if (SinkBlock->size() > SinkLoadInstsPerBlockThreshold) {
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if (SinkBlock->sizeWithoutDebugLargerThan(SinkLoadInstsPerBlockThreshold)) {
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LLVM_DEBUG(
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LLVM_DEBUG(
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dbgs() << "CycleSink: Not Sinking, block too large to analyse.\n");
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dbgs() << "CycleSink: Not Sinking, block too large to analyse.\n");
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return false;
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return false;
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@ -0,0 +1,137 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=machine-sink %s -o - | FileCheck %s
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# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=mir-debugify,machine-sink,mir-strip-debug %s -o - | FileCheck %s
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# Verify that machine-sink pass is debug invariant wrt to given input. Since
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# the pass examines MemOperands the IR is required for the original bug to
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# trigger.
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--- |
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@e = global i32 0, align 1
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@d = global i32 0, align 1
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@f = global i32 0, align 1
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@g = global i32 0, align 1
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define i32 @l() {
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entry:
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br label %for.body
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for.body: ; preds = %h.exit, %entry
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%cmp = phi i1 [ true, %entry ], [ false, %h.exit ]
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%0 = load i32, ptr @d, align 1
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%tobool61.not.i = icmp eq i32 %0, 0
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%e.promoted44.i = load i32, ptr @e, align 1
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br i1 %tobool61.not.i, label %h.exit, label %for.cond13.preheader.preheader.i
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for.cond13.preheader.preheader.i: ; preds = %for.body
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%1 = load i32, ptr @f, align 1
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store i32 %1, ptr @g, align 1
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br label %h.exit
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h.exit: ; preds = %for.cond13.preheader.preheader.i, %for.body
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%.us-phi50.i = or i32 %e.promoted44.i, 4
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store i32 %.us-phi50.i, ptr @e, align 1
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %h.exit
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ret i32 undef
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}
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...
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---
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name: l
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr8 }
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- { id: 1, class: gr32 }
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- { id: 2, class: gr8 }
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- { id: 3, class: gr64 }
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- { id: 4, class: gr64 }
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- { id: 5, class: gr64 }
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- { id: 6, class: gr32 }
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- { id: 7, class: gr64 }
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- { id: 8, class: gr8 }
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- { id: 9, class: gr32 }
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- { id: 10, class: gr64 }
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- { id: 11, class: gr32 }
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- { id: 12, class: gr32 }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: l
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 1
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; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @d, $noreg :: (load (s64) from got)
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; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @e, $noreg :: (load (s64) from got)
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; CHECK-NEXT: [[MOV64rm2:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @f, $noreg :: (load (s64) from got)
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; CHECK-NEXT: [[MOV64rm3:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @g, $noreg :: (load (s64) from got)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.for.body:
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; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.2(0x50000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr8 = PHI [[MOV8ri]], %bb.0, %8, %bb.3
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; CHECK-NEXT: CMP32mi8 [[MOV64rm]], 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (dereferenceable load (s32) from @d, align 1)
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; CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.for.cond13.preheader.preheader.i:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[MOV64rm2]], 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @f, align 1)
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; CHECK-NEXT: MOV32mr [[MOV64rm3]], 1, $noreg, 0, $noreg, killed [[MOV32rm]] :: (store (s32) into @g, align 1)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.h.exit:
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; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV64rm1]], 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @e, align 1)
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; CHECK-NEXT: [[OR32ri8_:%[0-9]+]]:gr32 = OR32ri8 [[MOV32rm1]], 4, implicit-def dead $eflags
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; CHECK-NEXT: MOV32mr [[MOV64rm1]], 1, $noreg, 0, $noreg, killed [[OR32ri8_]] :: (store (s32) into @e, align 1)
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; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32r0_]].sub_8bit
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; CHECK-NEXT: TEST8ri [[PHI]], 1, implicit-def $eflags
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; CHECK-NEXT: JCC_1 %bb.1, 5, implicit $eflags
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; CHECK-NEXT: JMP_1 %bb.4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4.for.end:
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; CHECK-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
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; CHECK-NEXT: $eax = COPY [[DEF]]
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; CHECK-NEXT: RET 0, $eax
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bb.0.entry:
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%2:gr8 = MOV8ri 1
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%3:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @d, $noreg :: (load (s64) from got)
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%4:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @e, $noreg :: (load (s64) from got)
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%5:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @f, $noreg :: (load (s64) from got)
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%7:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @g, $noreg :: (load (s64) from got)
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bb.1.for.body:
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successors: %bb.3(0x30000000), %bb.2(0x50000000)
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%0:gr8 = PHI %2, %bb.0, %8, %bb.3
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CMP32mi8 %3, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (dereferenceable load (s32) from @d, align 1)
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%1:gr32 = MOV32rm %4, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @e, align 1)
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JCC_1 %bb.3, 4, implicit $eflags
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JMP_1 %bb.2
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bb.2.for.cond13.preheader.preheader.i:
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%6:gr32 = MOV32rm %5, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @f, align 1)
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MOV32mr %7, 1, $noreg, 0, $noreg, killed %6 :: (store (s32) into @g, align 1)
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bb.3.h.exit:
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successors: %bb.1(0x7c000000), %bb.4(0x04000000)
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%9:gr32 = OR32ri8 %1, 4, implicit-def dead $eflags
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MOV32mr %4, 1, $noreg, 0, $noreg, killed %9 :: (store (s32) into @e, align 1)
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%11:gr32 = MOV32r0 implicit-def dead $eflags
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%8:gr8 = COPY %11.sub_8bit
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TEST8ri %0, 1, implicit-def $eflags
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JCC_1 %bb.1, 5, implicit $eflags
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JMP_1 %bb.4
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bb.4.for.end:
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%12:gr32 = IMPLICIT_DEF
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$eax = COPY %12
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RET 0, $eax
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...
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