forked from OSchip/llvm-project
[mips] Small update to the logic behind the expansion of assembly pseudo instructions.
Summary: The functions that do the expansion now return false on success and true otherwise. This is so we can catch some errors during the expansion (e.g.: immediate too large). The next patch adds some test cases. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4214 llvm-svn: 211269
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@ -116,14 +116,20 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool needsExpansion(MCInst &Inst);
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void expandInstruction(MCInst &Inst, SMLoc IDLoc,
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// Expands assembly pseudo instructions.
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// Returns false on success, true otherwise.
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bool expandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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bool expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
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bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
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bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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void expandMemInst(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions, bool isLoad,
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bool isImmOpnd);
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@ -965,7 +971,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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} // if load/store
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if (needsExpansion(Inst))
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expandInstruction(Inst, IDLoc, Instructions);
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return expandInstruction(Inst, IDLoc, Instructions);
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else
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Instructions.push_back(Inst);
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@ -984,9 +990,11 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
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}
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}
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void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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switch (Inst.getOpcode()) {
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default: assert(0 && "unimplemented expansion");
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return true;
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case Mips::LoadImm32Reg:
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return expandLoadImm(Inst, IDLoc, Instructions);
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case Mips::LoadAddr32Imm:
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@ -996,7 +1004,7 @@ void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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}
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}
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void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst tmpInst;
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const MCOperand &ImmOp = Inst.getOperand(1);
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@ -1038,9 +1046,10 @@ void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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tmpInst.setLoc(IDLoc);
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Instructions.push_back(tmpInst);
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}
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return false;
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}
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void
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bool
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MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst tmpInst;
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@ -1081,9 +1090,10 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
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tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
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Instructions.push_back(tmpInst);
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}
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return false;
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}
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void
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bool
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MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst tmpInst;
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@ -1115,6 +1125,7 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
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tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
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Instructions.push_back(tmpInst);
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}
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return false;
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}
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void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
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