forked from OSchip/llvm-project
Revamp the ICC/FCC reading instructions to be parameterized in terms of the
SPARC condition codes, not in terms of the DAG condcodes. This allows us to write nice clean patterns for cmovs/branches. llvm-svn: 25815
This commit is contained in:
Chris Lattner
parent
33a79cae7c
commit
37faeb2b02
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@ -50,6 +50,123 @@ namespace V8ISD {
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};
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}
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// Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
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// values must be kept in sync with the ones in the .td file.
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namespace V8CC {
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enum CondCodes {
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//ICC_A = 8 , // Always
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//ICC_N = 0 , // Never
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ICC_NE = 9 , // Not Equal
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ICC_E = 1 , // Equal
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ICC_G = 10 , // Greater
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ICC_LE = 2 , // Less or Equal
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ICC_GE = 11 , // Greater or Equal
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ICC_L = 3 , // Less
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ICC_GU = 12 , // Greater Unsigned
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ICC_LEU = 4 , // Less or Equal Unsigned
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ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned
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ICC_CS = 5 , // Carry Set/Less Unsigned
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ICC_POS = 14 , // Positive
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ICC_NEG = 6 , // Negative
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ICC_VC = 15 , // Overflow Clear
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ICC_VS = 7 , // Overflow Set
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//FCC_A = 8+16, // Always
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//FCC_N = 0+16, // Never
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FCC_U = 7+16, // Unordered
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FCC_G = 6+16, // Greater
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FCC_UG = 5+16, // Unordered or Greater
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FCC_L = 4+16, // Less
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FCC_UL = 3+16, // Unordered or Less
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FCC_LG = 2+16, // Less or Greater
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FCC_NE = 1+16, // Not Equal
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FCC_E = 9+16, // Equal
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FCC_UE = 10+16, // Unordered or Equal
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FCC_GE = 11+16, // Greater or Equal
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FCC_UGE = 12+16, // Unordered or Greater or Equal
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FCC_LE = 13+16, // Less or Equal
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FCC_ULE = 14+16, // Unordered or Less or Equal
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FCC_O = 15+16, // Ordered
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};
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}
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/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
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/// condition.
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static V8CC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Unknown integer condition code!");
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case ISD::SETEQ: return V8CC::ICC_E;
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case ISD::SETNE: return V8CC::ICC_NE;
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case ISD::SETLT: return V8CC::ICC_L;
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case ISD::SETGT: return V8CC::ICC_G;
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case ISD::SETLE: return V8CC::ICC_LE;
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case ISD::SETGE: return V8CC::ICC_GE;
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case ISD::SETULT: return V8CC::ICC_CS;
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case ISD::SETULE: return V8CC::ICC_LEU;
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case ISD::SETUGT: return V8CC::ICC_GU;
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case ISD::SETUGE: return V8CC::ICC_CC;
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}
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}
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/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
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/// FCC condition.
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static V8CC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Unknown fp condition code!");
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case ISD::SETEQ: return V8CC::FCC_E;
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case ISD::SETNE: return V8CC::FCC_NE;
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case ISD::SETLT: return V8CC::FCC_L;
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case ISD::SETGT: return V8CC::FCC_G;
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case ISD::SETLE: return V8CC::FCC_LE;
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case ISD::SETGE: return V8CC::FCC_GE;
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case ISD::SETULT: return V8CC::FCC_UL;
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case ISD::SETULE: return V8CC::FCC_ULE;
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case ISD::SETUGT: return V8CC::FCC_UG;
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case ISD::SETUGE: return V8CC::FCC_UGE;
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case ISD::SETUO: return V8CC::FCC_U;
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case ISD::SETO: return V8CC::FCC_O;
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case ISD::SETONE: return V8CC::FCC_LG;
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case ISD::SETUEQ: return V8CC::FCC_UE;
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}
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}
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static unsigned SPARCCondCodeToBranchInstr(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case V8CC::ICC_NE: return V8::BNE;
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case V8CC::ICC_E: return V8::BE;
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case V8CC::ICC_G: return V8::BG;
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case V8CC::ICC_LE: return V8::BLE;
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case V8CC::ICC_GE: return V8::BGE;
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case V8CC::ICC_L: return V8::BL;
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case V8CC::ICC_GU: return V8::BGU;
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case V8CC::ICC_LEU: return V8::BLEU;
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case V8CC::ICC_CC: return V8::BCC;
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case V8CC::ICC_CS: return V8::BCS;
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case V8CC::ICC_POS: return V8::BPOS;
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case V8CC::ICC_NEG: return V8::BNEG;
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case V8CC::ICC_VC: return V8::BVC;
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case V8CC::ICC_VS: return V8::BVS;
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case V8CC::FCC_U: return V8::FBU;
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case V8CC::FCC_G: return V8::FBG;
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case V8CC::FCC_UG: return V8::FBUG;
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case V8CC::FCC_L: return V8::FBL;
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case V8CC::FCC_UL: return V8::FBUL;
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case V8CC::FCC_LG: return V8::FBLG;
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case V8CC::FCC_NE: return V8::FBNE;
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case V8CC::FCC_E: return V8::FBE;
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case V8CC::FCC_UE: return V8::FBUE;
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case V8CC::FCC_GE: return V8::FBGE;
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case V8CC::FCC_UGE: return V8::FBUGE;
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case V8CC::FCC_LE: return V8::FBLE;
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case V8CC::FCC_ULE: return V8::FBULE;
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case V8CC::FCC_O: return V8::FBO;
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}
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}
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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@ -645,7 +762,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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case ISD::BR_CC: {
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SDOperand Chain = Op.getOperand(0);
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SDOperand CC = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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@ -659,19 +776,22 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(LHS);
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Ops.push_back(RHS);
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SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
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return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
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SDOperand CCN = DAG.getConstant(IntCondCCodeToICC(CC), MVT::i32);
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return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CCN, Cond);
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} else {
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SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
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return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
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SDOperand CCN = DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32);
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return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CCN, Cond);
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}
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}
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case ISD::SELECT_CC: {
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SDOperand LHS = Op.getOperand(0);
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SDOperand RHS = Op.getOperand(1);
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unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDOperand TrueVal = Op.getOperand(2);
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SDOperand FalseVal = Op.getOperand(3);
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unsigned Opc, V8CC = ~0U;
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// If this is a select_cc of a "setcc", and if the setcc got lowered into
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// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
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if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0&&
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@ -685,13 +805,12 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
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cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
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SDOperand CMPCC = LHS.getOperand(3);
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CC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
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V8CC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
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LHS = CMPCC.getOperand(0);
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RHS = CMPCC.getOperand(1);
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}
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SDOperand CompareFlag;
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unsigned Opc;
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if (LHS.getValueType() == MVT::i32) {
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(LHS.getValueType()); // subcc returns a value
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@ -701,12 +820,14 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(RHS);
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CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
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Opc = V8ISD::SELECT_ICC;
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if (V8CC == ~0U) V8CC = IntCondCCodeToICC(CC);
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} else {
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CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
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Opc = V8ISD::SELECT_FCC;
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if (V8CC == ~0U) V8CC = FPCondCCodeToFCC(CC);
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}
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return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
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DAG.getConstant(CC, MVT::i32), CompareFlag);
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DAG.getConstant(V8CC, MVT::i32), CompareFlag);
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}
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case ISD::VASTART: {
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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@ -759,42 +880,11 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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case V8::SELECT_CC_Int_ICC:
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case V8::SELECT_CC_FP_ICC:
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case V8::SELECT_CC_DFP_ICC:
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// Integer compare.
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switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
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default: assert(0 && "Unknown integer condition code!");
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case ISD::SETEQ: BROpcode = V8::BE; break;
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case ISD::SETNE: BROpcode = V8::BNE; break;
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case ISD::SETLT: BROpcode = V8::BL; break;
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case ISD::SETGT: BROpcode = V8::BG; break;
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case ISD::SETLE: BROpcode = V8::BLE; break;
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case ISD::SETGE: BROpcode = V8::BGE; break;
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case ISD::SETULT: BROpcode = V8::BCS; break;
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case ISD::SETULE: BROpcode = V8::BLEU; break;
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case ISD::SETUGT: BROpcode = V8::BGU; break;
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case ISD::SETUGE: BROpcode = V8::BCC; break;
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}
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break;
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case V8::SELECT_CC_Int_FCC:
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case V8::SELECT_CC_FP_FCC:
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case V8::SELECT_CC_DFP_FCC:
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// FP compare.
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switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
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default: assert(0 && "Unknown fp condition code!");
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case ISD::SETEQ: BROpcode = V8::FBE; break;
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case ISD::SETNE: BROpcode = V8::FBNE; break;
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case ISD::SETLT: BROpcode = V8::FBL; break;
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case ISD::SETGT: BROpcode = V8::FBG; break;
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case ISD::SETLE: BROpcode = V8::FBLE; break;
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case ISD::SETGE: BROpcode = V8::FBGE; break;
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case ISD::SETULT: BROpcode = V8::FBUL; break;
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case ISD::SETULE: BROpcode = V8::FBULE; break;
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case ISD::SETUGT: BROpcode = V8::FBUG; break;
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case ISD::SETUGE: BROpcode = V8::FBUGE; break;
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case ISD::SETUO: BROpcode = V8::FBU; break;
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case ISD::SETO: BROpcode = V8::FBO; break;
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case ISD::SETONE: BROpcode = V8::FBLG; break;
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case ISD::SETUEQ: BROpcode = V8::FBUE; break;
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}
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V8CC::CondCodes CC = (V8CC::CondCodes)MI->getOperand(3).getImmedValue();
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BROpcode = SPARCCondCodeToBranchInstr(CC);
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break;
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}
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@ -84,7 +84,7 @@ def calltarget : Operand<i32>;
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def SDTV8cmpfcc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
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def SDTV8brcc :
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SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
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SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
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SDTCisVT<2, FlagVT>]>;
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def SDTV8selectcc :
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SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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@ -121,6 +121,43 @@ def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
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def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
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[SDNPHasChain, SDNPOptInFlag]>;
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//===----------------------------------------------------------------------===//
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// SPARC Flag Conditions
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//===----------------------------------------------------------------------===//
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// Note that these values must be kept in sync with the V8CC::CondCode enum
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// values.
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def ICC_NE : PatLeaf<(i32 9)>; // Not Equal
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def ICC_E : PatLeaf<(i32 1)>; // Equal
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def ICC_G : PatLeaf<(i32 10)>; // Greater
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def ICC_LE : PatLeaf<(i32 2)>; // Less or Equal
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def ICC_GE : PatLeaf<(i32 11)>; // Greater or Equal
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def ICC_L : PatLeaf<(i32 3)>; // Less
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def ICC_GU : PatLeaf<(i32 12)>; // Greater Unsigned
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def ICC_LEU : PatLeaf<(i32 4)>; // Less or Equal Unsigned
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def ICC_CC : PatLeaf<(i32 13)>; // Carry Clear/Great or Equal Unsigned
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def ICC_CS : PatLeaf<(i32 5)>; // Carry Set/Less Unsigned
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def ICC_POS : PatLeaf<(i32 14)>; // Positive
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def ICC_NEG : PatLeaf<(i32 6)>; // Negative
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def ICC_VC : PatLeaf<(i32 15)>; // Overflow Clear
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def ICC_VS : PatLeaf<(i32 7)>; // Overflow Set
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def FCC_U : PatLeaf<(i32 23)>; // Unordered
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def FCC_G : PatLeaf<(i32 22)>; // Greater
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def FCC_UG : PatLeaf<(i32 21)>; // Unordered or Greater
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def FCC_L : PatLeaf<(i32 20)>; // Less
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def FCC_UL : PatLeaf<(i32 19)>; // Unordered or Less
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def FCC_LG : PatLeaf<(i32 18)>; // Less or Greater
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def FCC_NE : PatLeaf<(i32 17)>; // Not Equal
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def FCC_E : PatLeaf<(i32 25)>; // Equal
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def FCC_UE : PatLeaf<(i32 24)>; // Unordered or Equal
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def FCC_GE : PatLeaf<(i32 25)>; // Greater or Equal
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def FCC_UGE : PatLeaf<(i32 26)>; // Unordered or Greater or Equal
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def FCC_LE : PatLeaf<(i32 27)>; // Less or Equal
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def FCC_ULE : PatLeaf<(i32 28)>; // Unordered or Less or Equal
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def FCC_O : PatLeaf<(i32 29)>; // Ordered
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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@ -498,34 +535,48 @@ let isBarrier = 1 in
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[(br bb:$dst)]>;
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def BNE : BranchV8<0b1001, (ops brtarget:$dst),
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"bne $dst",
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[(V8bricc bb:$dst, SETNE, ICC)]>;
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[(V8bricc bb:$dst, ICC_NE, ICC)]>;
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def BE : BranchV8<0b0001, (ops brtarget:$dst),
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"be $dst",
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[(V8bricc bb:$dst, SETEQ, ICC)]>;
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[(V8bricc bb:$dst, ICC_E, ICC)]>;
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def BG : BranchV8<0b1010, (ops brtarget:$dst),
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"bg $dst",
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[(V8bricc bb:$dst, SETGT, ICC)]>;
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[(V8bricc bb:$dst, ICC_G, ICC)]>;
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def BLE : BranchV8<0b0010, (ops brtarget:$dst),
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"ble $dst",
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[(V8bricc bb:$dst, SETLE, ICC)]>;
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[(V8bricc bb:$dst, ICC_LE, ICC)]>;
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def BGE : BranchV8<0b1011, (ops brtarget:$dst),
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"bge $dst",
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[(V8bricc bb:$dst, SETGE, ICC)]>;
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[(V8bricc bb:$dst, ICC_GE, ICC)]>;
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def BL : BranchV8<0b0011, (ops brtarget:$dst),
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"bl $dst",
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[(V8bricc bb:$dst, SETLT, ICC)]>;
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[(V8bricc bb:$dst, ICC_L, ICC)]>;
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def BGU : BranchV8<0b1100, (ops brtarget:$dst),
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"bgu $dst",
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[(V8bricc bb:$dst, SETUGT, ICC)]>;
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[(V8bricc bb:$dst, ICC_GU, ICC)]>;
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def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
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"bleu $dst",
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[(V8bricc bb:$dst, SETULE, ICC)]>;
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[(V8bricc bb:$dst, ICC_LEU, ICC)]>;
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def BCC : BranchV8<0b1101, (ops brtarget:$dst),
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"bcc $dst",
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[(V8bricc bb:$dst, SETUGE, ICC)]>;
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[(V8bricc bb:$dst, ICC_CC, ICC)]>;
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def BCS : BranchV8<0b0101, (ops brtarget:$dst),
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"bcs $dst",
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[(V8bricc bb:$dst, SETULT, ICC)]>;
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[(V8bricc bb:$dst, ICC_CS, ICC)]>;
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def BPOS : BranchV8<0b1110, (ops brtarget:$dst),
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"bpos $dst",
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[(V8bricc bb:$dst, ICC_POS, ICC)]>;
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def BNEG : BranchV8<0b0110, (ops brtarget:$dst),
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"bneg $dst",
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[(V8bricc bb:$dst, ICC_NEG, ICC)]>;
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def BVC : BranchV8<0b1111, (ops brtarget:$dst),
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"bvc $dst",
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[(V8bricc bb:$dst, ICC_VC, ICC)]>;
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def BVS : BranchV8<0b0111, (ops brtarget:$dst),
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"bvs $dst",
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[(V8bricc bb:$dst, ICC_VS, ICC)]>;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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@ -540,46 +591,46 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
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"fbu $dst",
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[(V8brfcc bb:$dst, SETUO, FCC)]>;
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[(V8brfcc bb:$dst, FCC_U, FCC)]>;
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def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
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"fbg $dst",
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||||
[(V8brfcc bb:$dst, SETGT, FCC)]>;
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[(V8brfcc bb:$dst, FCC_G, FCC)]>;
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def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
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||||
"fbug $dst",
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||||
[(V8brfcc bb:$dst, SETUGT, FCC)]>;
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||||
[(V8brfcc bb:$dst, FCC_UG, FCC)]>;
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def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
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||||
"fbl $dst",
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[(V8brfcc bb:$dst, SETLT, FCC)]>;
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[(V8brfcc bb:$dst, FCC_L, FCC)]>;
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||||
def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
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||||
"fbul $dst",
|
||||
[(V8brfcc bb:$dst, SETULT, FCC)]>;
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||||
[(V8brfcc bb:$dst, FCC_UL, FCC)]>;
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||||
def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
|
||||
"fblg $dst",
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||||
[(V8brfcc bb:$dst, SETONE, FCC)]>;
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||||
[(V8brfcc bb:$dst, FCC_LG, FCC)]>;
|
||||
def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
|
||||
"fbne $dst",
|
||||
[(V8brfcc bb:$dst, SETNE, FCC)]>;
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||||
[(V8brfcc bb:$dst, FCC_NE, FCC)]>;
|
||||
def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
|
||||
"fbe $dst",
|
||||
[(V8brfcc bb:$dst, SETEQ, FCC)]>;
|
||||
[(V8brfcc bb:$dst, FCC_E, FCC)]>;
|
||||
def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
|
||||
"fbue $dst",
|
||||
[(V8brfcc bb:$dst, SETUEQ, FCC)]>;
|
||||
[(V8brfcc bb:$dst, FCC_UE, FCC)]>;
|
||||
def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
|
||||
"fbge $dst",
|
||||
[(V8brfcc bb:$dst, SETGE, FCC)]>;
|
||||
[(V8brfcc bb:$dst, FCC_GE, FCC)]>;
|
||||
def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
|
||||
"fbuge $dst",
|
||||
[(V8brfcc bb:$dst, SETUGE, FCC)]>;
|
||||
[(V8brfcc bb:$dst, FCC_UGE, FCC)]>;
|
||||
def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
|
||||
"fble $dst",
|
||||
[(V8brfcc bb:$dst, SETLE, FCC)]>;
|
||||
[(V8brfcc bb:$dst, FCC_LE, FCC)]>;
|
||||
def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
|
||||
"fbule $dst",
|
||||
[(V8brfcc bb:$dst, SETULE, FCC)]>;
|
||||
[(V8brfcc bb:$dst, FCC_ULE, FCC)]>;
|
||||
def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
|
||||
"fbo $dst",
|
||||
[(V8brfcc bb:$dst, SETO, FCC)]>;
|
||||
[(V8brfcc bb:$dst, FCC_O, FCC)]>;
|
||||
|
||||
|
||||
|
||||
|
|
@ -742,11 +793,11 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
|
|||
def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movne %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, 22, ICC))]>;
|
||||
def MOVEQ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"move %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, 17, ICC))]>;
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_NE, ICC))]>;
|
||||
def MOVE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"move %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_E, ICC))]>;
|
||||
}
|
||||
|
||||
// Floating-Point Move Instructions, p. 164 of the V9 manual.
|
||||
|
|
|
|||
Loading…
Reference in New Issue