forked from OSchip/llvm-project
[AArch64] Identify SAD pattern
(ABS (SUB (EXTEND a), (EXTEND b))) to ZERO_EXTEND((UABD a, b)) (ABS (SUB (SIGN_EXTEND a), (SIGN_EXTEND b))) to ZERO_EXTEND((SABD a, b)) This partially solves the bug: https://bugs.llvm.org/show_bug.cgi?id=46888 Meta ticket: https://bugs.llvm.org/show_bug.cgi?id=46929 Differential Revision: https://reviews.llvm.org/D88742
This commit is contained in:
Vinay Madhusudan
parent
25a8881b72
commit
37dce7475b
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@ -759,6 +759,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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// Vector add and sub nodes may conceal a high-half opportunity.
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// Also, try to fold ADD into CSINC/CSINV..
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::ABS);
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setTargetDAGCombine(ISD::SUB);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::XOR);
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@ -1830,6 +1831,8 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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MAKE_CASE(AArch64ISD::STNP)
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MAKE_CASE(AArch64ISD::DUP_MERGE_PASSTHRU)
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MAKE_CASE(AArch64ISD::INDEX_VECTOR)
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MAKE_CASE(AArch64ISD::UABD)
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MAKE_CASE(AArch64ISD::SABD)
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}
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#undef MAKE_CASE
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return nullptr;
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@ -3659,6 +3662,15 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return DAG.getNode(Opcode, dl, Op.getValueType(), Op.getOperand(1),
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Op.getOperand(2));
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}
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case Intrinsic::aarch64_neon_uabd: {
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return DAG.getNode(AArch64ISD::UABD, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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}
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case Intrinsic::aarch64_neon_sabd: {
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return DAG.getNode(AArch64ISD::SABD, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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}
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}
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}
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@ -11050,6 +11062,48 @@ static SDValue performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG,
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return DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), Dot);
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}
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// Given a ABS node, detect the following pattern:
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// (ABS (SUB (EXTEND a), (EXTEND b))).
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// Generates UABD/SABD instruction.
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static SDValue performABSCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const AArch64Subtarget *Subtarget) {
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SDValue AbsOp1 = N->getOperand(0);
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SDValue Op0, Op1;
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if (AbsOp1.getOpcode() != ISD::SUB)
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return SDValue();
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Op0 = AbsOp1.getOperand(0);
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Op1 = AbsOp1.getOperand(1);
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unsigned Opc0 = Op0.getOpcode();
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// Check if the operands of the sub are (zero|sign)-extended.
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if (Opc0 != Op1.getOpcode() ||
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(Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND))
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return SDValue();
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EVT VectorT1 = Op0.getOperand(0).getValueType();
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EVT VectorT2 = Op1.getOperand(0).getValueType();
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// Check if vectors are of same type and valid size.
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uint64_t Size = VectorT1.getFixedSizeInBits();
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if (VectorT1 != VectorT2 || (Size != 64 && Size != 128))
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return SDValue();
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// Check if vector element types are valid.
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EVT VT1 = VectorT1.getVectorElementType();
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if (VT1 != MVT::i8 && VT1 != MVT::i16 && VT1 != MVT::i32)
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return SDValue();
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Op0 = Op0.getOperand(0);
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Op1 = Op1.getOperand(0);
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unsigned ABDOpcode =
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(Opc0 == ISD::SIGN_EXTEND) ? AArch64ISD::SABD : AArch64ISD::UABD;
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SDValue ABD =
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DAG.getNode(ABDOpcode, SDLoc(N), Op0->getValueType(0), Op0, Op1);
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), ABD);
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}
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static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const AArch64Subtarget *Subtarget) {
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@ -12339,8 +12393,8 @@ static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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SDValue LHS = N->getOperand(1);
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SDValue RHS = N->getOperand(2);
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SDValue LHS = N->getOperand((IID == Intrinsic::not_intrinsic) ? 0 : 1);
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SDValue RHS = N->getOperand((IID == Intrinsic::not_intrinsic) ? 1 : 2);
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assert(LHS.getValueType().is64BitVector() &&
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RHS.getValueType().is64BitVector() &&
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"unexpected shape for long operation");
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@ -12358,6 +12412,9 @@ static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
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return SDValue();
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}
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if (IID == Intrinsic::not_intrinsic)
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return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), LHS, RHS);
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
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N->getOperand(0), LHS, RHS);
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}
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@ -12868,18 +12925,15 @@ static SDValue performExtendCombine(SDNode *N,
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// helps the backend to decide that an sabdl2 would be useful, saving a real
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// extract_high operation.
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if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
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N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
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(N->getOperand(0).getOpcode() == AArch64ISD::UABD ||
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N->getOperand(0).getOpcode() == AArch64ISD::SABD)) {
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SDNode *ABDNode = N->getOperand(0).getNode();
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unsigned IID = getIntrinsicID(ABDNode);
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if (IID == Intrinsic::aarch64_neon_sabd ||
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IID == Intrinsic::aarch64_neon_uabd) {
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SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
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if (!NewABD.getNode())
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return SDValue();
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SDValue NewABD =
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tryCombineLongOpWithDup(Intrinsic::not_intrinsic, ABDNode, DCI, DAG);
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if (!NewABD.getNode())
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return SDValue();
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
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NewABD);
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}
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), NewABD);
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}
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// This is effectively a custom type legalization for AArch64.
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@ -14672,6 +14726,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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default:
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LLVM_DEBUG(dbgs() << "Custom combining: skipping\n");
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break;
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case ISD::ABS:
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return performABSCombine(N, DAG, DCI, Subtarget);
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case ISD::ADD:
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case ISD::SUB:
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return performAddSubLongCombine(N, DCI, DAG);
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@ -225,6 +225,10 @@ enum NodeType : unsigned {
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SRHADD,
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URHADD,
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// Absolute difference
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UABD,
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SABD,
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// Vector across-lanes min/max
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// Only the lower result lane is defined.
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SMINV,
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@ -559,6 +559,16 @@ def AArch64urhadd : SDNode<"AArch64ISD::URHADD", SDT_AArch64binvec>;
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def AArch64shadd : SDNode<"AArch64ISD::SHADD", SDT_AArch64binvec>;
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def AArch64uhadd : SDNode<"AArch64ISD::UHADD", SDT_AArch64binvec>;
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def AArch64uabd_n : SDNode<"AArch64ISD::UABD", SDT_AArch64binvec>;
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def AArch64sabd_n : SDNode<"AArch64ISD::SABD", SDT_AArch64binvec>;
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def AArch64uabd : PatFrags<(ops node:$lhs, node:$rhs),
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[(AArch64uabd_n node:$lhs, node:$rhs),
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(int_aarch64_neon_uabd node:$lhs, node:$rhs)]>;
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def AArch64sabd : PatFrags<(ops node:$lhs, node:$rhs),
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[(AArch64sabd_n node:$lhs, node:$rhs),
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(int_aarch64_neon_sabd node:$lhs, node:$rhs)]>;
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def SDT_AArch64SETTAG : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
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def AArch64stg : SDNode<"AArch64ISD::STG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def AArch64stzg : SDNode<"AArch64ISD::STZG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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@ -3812,7 +3822,7 @@ defm FMOV : FPMoveImmediate<"fmov">;
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//===----------------------------------------------------------------------===//
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defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
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int_aarch64_neon_uabd>;
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AArch64uabd>;
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// Match UABDL in log2-shuffle patterns.
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def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)),
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(zext (v8i8 V64:$opB))))),
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@ -4082,8 +4092,8 @@ defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", null_frag>;
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defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
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defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
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defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
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TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
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defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
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TriOpFrag<(add node:$LHS, (AArch64sabd node:$MHS, node:$RHS))> >;
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defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", AArch64sabd>;
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defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", AArch64shadd>;
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defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
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defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
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@ -4101,8 +4111,8 @@ defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
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defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
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defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
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defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
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TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
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defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
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TriOpFrag<(add node:$LHS, (AArch64uabd node:$MHS, node:$RHS))> >;
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defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", AArch64uabd>;
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defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", AArch64uhadd>;
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defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
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defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
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@ -4676,9 +4686,9 @@ defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn
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defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
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defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
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defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
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int_aarch64_neon_sabd>;
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AArch64sabd>;
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defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
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int_aarch64_neon_sabd>;
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AArch64sabd>;
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defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
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BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
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defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
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@ -4699,7 +4709,7 @@ defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
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defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
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BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
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defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
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int_aarch64_neon_uabd>;
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AArch64uabd>;
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defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
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BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
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defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
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@ -142,11 +142,11 @@ define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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}
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declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
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declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
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define i16 @uabdl8h_rdx(<16 x i8>* %a, <16 x i8>* %b) {
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; CHECK-LABEL: uabdl8h_rdx
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; CHECK: uabdl2.8h
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; CHECK: uabdl.8h
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define i16 @uabd16b_rdx(<16 x i8>* %a, <16 x i8>* %b) {
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; CHECK-LABEL: uabd16b_rdx
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; CHECK: uabd.16b
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%aload = load <16 x i8>, <16 x i8>* %a, align 1
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%bload = load <16 x i8>, <16 x i8>* %b, align 1
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%aext = zext <16 x i8> %aload to <16 x i16>
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@ -159,12 +159,39 @@ define i16 @uabdl8h_rdx(<16 x i8>* %a, <16 x i8>* %b) {
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ret i16 %reduced_v
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}
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declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
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define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: uabd16b_rdx_i32
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; CHECK: uabd.16b
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%aext = zext <16 x i8> %a to <16 x i32>
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%bext = zext <16 x i8> %b to <16 x i32>
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%abdiff = sub nsw <16 x i32> %aext, %bext
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%abcmp = icmp slt <16 x i32> %abdiff, zeroinitializer
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%ababs = sub nsw <16 x i32> zeroinitializer, %abdiff
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%absel = select <16 x i1> %abcmp, <16 x i32> %ababs, <16 x i32> %abdiff
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%reduced_v = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %absel)
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ret i32 %reduced_v
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}
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define i32 @uabdl4s_rdx(<8 x i16>* %a, <8 x i16>* %b) {
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; CHECK-LABEL: uabdl4s_rdx
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; CHECK: uabdl2.4s
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; CHECK: uabdl.4s
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define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: sabd16b_rdx_i32
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; CHECK: sabd.16b
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%aext = sext <16 x i8> %a to <16 x i32>
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%bext = sext <16 x i8> %b to <16 x i32>
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%abdiff = sub nsw <16 x i32> %aext, %bext
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%abcmp = icmp slt <16 x i32> %abdiff, zeroinitializer
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%ababs = sub nsw <16 x i32> zeroinitializer, %abdiff
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%absel = select <16 x i1> %abcmp, <16 x i32> %ababs, <16 x i32> %abdiff
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%reduced_v = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %absel)
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ret i32 %reduced_v
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}
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declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
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declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
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define i32 @uabd8h_rdx(<8 x i16>* %a, <8 x i16>* %b) {
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; CHECK-LABEL: uabd8h_rdx
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; CHECK: uabd.8h
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%aload = load <8 x i16>, <8 x i16>* %a, align 1
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%bload = load <8 x i16>, <8 x i16>* %b, align 1
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%aext = zext <8 x i16> %aload to <8 x i32>
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@ -177,12 +204,38 @@ define i32 @uabdl4s_rdx(<8 x i16>* %a, <8 x i16>* %b) {
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ret i32 %reduced_v
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}
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declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
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define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: sabd8h_rdx
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; CHECK: sabd.8h
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%aext = sext <8 x i16> %a to <8 x i32>
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%bext = sext <8 x i16> %b to <8 x i32>
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%abdiff = sub nsw <8 x i32> %aext, %bext
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%abcmp = icmp slt <8 x i32> %abdiff, zeroinitializer
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%ababs = sub nsw <8 x i32> zeroinitializer, %abdiff
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%absel = select <8 x i1> %abcmp, <8 x i32> %ababs, <8 x i32> %abdiff
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%reduced_v = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %absel)
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ret i32 %reduced_v
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}
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define i64 @uabdl2d_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {
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; CHECK: uabdl2d_rdx
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; CHECK: uabdl2.2d
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; CHECK: uabdl.2d
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define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: uabdl4s_rdx_i32
|
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; CHECK: uabdl.4s
|
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%aext = zext <4 x i16> %a to <4 x i32>
|
||||
%bext = zext <4 x i16> %b to <4 x i32>
|
||||
%abdiff = sub nsw <4 x i32> %aext, %bext
|
||||
%abcmp = icmp slt <4 x i32> %abdiff, zeroinitializer
|
||||
%ababs = sub nsw <4 x i32> zeroinitializer, %abdiff
|
||||
%absel = select <4 x i1> %abcmp, <4 x i32> %ababs, <4 x i32> %abdiff
|
||||
%reduced_v = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %absel)
|
||||
ret i32 %reduced_v
|
||||
}
|
||||
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
|
||||
define i64 @uabd4s_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {
|
||||
; CHECK: uabd4s_rdx
|
||||
; CHECK: uabd.4s
|
||||
%aload = load <4 x i32>, <4 x i32>* %a, align 1
|
||||
%bload = load <4 x i32>, <4 x i32>* %b, align 1
|
||||
%aext = zext <4 x i32> %aload to <4 x i64>
|
||||
|
|
@ -195,6 +248,32 @@ define i64 @uabdl2d_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {
|
|||
ret i64 %reduced_v
|
||||
}
|
||||
|
||||
define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {
|
||||
; CHECK: sabd4s_rdx
|
||||
; CHECK: sabd.4s
|
||||
%aext = sext <4 x i32> %a to <4 x i64>
|
||||
%bext = sext <4 x i32> %b to <4 x i64>
|
||||
%abdiff = sub nsw <4 x i64> %aext, %bext
|
||||
%abcmp = icmp slt <4 x i64> %abdiff, zeroinitializer
|
||||
%ababs = sub nsw <4 x i64> zeroinitializer, %abdiff
|
||||
%absel = select <4 x i1> %abcmp, <4 x i64> %ababs, <4 x i64> %abdiff
|
||||
%reduced_v = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %absel)
|
||||
ret i64 %reduced_v
|
||||
}
|
||||
|
||||
define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
|
||||
; CHECK-LABEL: uabdl2d_rdx_i64
|
||||
; CHECK: uabdl.2d
|
||||
%aext = zext <2 x i32> %a to <2 x i64>
|
||||
%bext = zext <2 x i32> %b to <2 x i64>
|
||||
%abdiff = sub nsw <2 x i64> %aext, %bext
|
||||
%abcmp = icmp slt <2 x i64> %abdiff, zeroinitializer
|
||||
%ababs = sub nsw <2 x i64> zeroinitializer, %abdiff
|
||||
%absel = select <2 x i1> %abcmp, <2 x i64> %ababs, <2 x i64> %abdiff
|
||||
%reduced_v = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %absel)
|
||||
ret i64 %reduced_v
|
||||
}
|
||||
|
||||
define <2 x float> @fabd_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
;CHECK-LABEL: fabd_2s:
|
||||
;CHECK: fabd.2s
|
||||
|
|
|
|||
Loading…
Reference in New Issue