From 37d68e4599677a57d0addf747ff3c30dfe39b14a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Thu, 6 Sep 2018 23:55:34 +0000
Subject: [PATCH] [X86] Add a test case showing failure to use the RMW form of
 ADC when the load is in operand 1 going into isel.

The ADC instruction is commutable, but we only have RMW isel patterns with a load on the left hand side. Nothing will canonicalize loads to the LHS on these ops. So we need two patterns.

llvm-svn: 341605
---
 llvm/test/CodeGen/X86/addcarry.ll | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll
index f2e7a7ecc1a5..3f9391c917b4 100644
--- a/llvm/test/CodeGen/X86/addcarry.ll
+++ b/llvm/test/CodeGen/X86/addcarry.ll
@@ -14,6 +14,34 @@ entry:
   ret i128 %0
 }
 
+define void @add128_rmw(i128* %a, i128 %b) nounwind {
+; CHECK-LABEL: add128_rmw:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq %rsi, (%rdi)
+; CHECK-NEXT:    adcq %rdx, 8(%rdi)
+; CHECK-NEXT:    retq
+entry:
+  %0 = load i128, i128* %a
+  %1 = add i128 %0, %b
+  store i128 %1, i128* %a
+  ret void
+}
+
+define void @add128_rmw2(i128 %a, i128* %b) nounwind {
+; CHECK-LABEL: add128_rmw2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq (%rdx), %rdi
+; CHECK-NEXT:    adcq 8(%rdx), %rsi
+; CHECK-NEXT:    movq %rdi, (%rdx)
+; CHECK-NEXT:    movq %rsi, 8(%rdx)
+; CHECK-NEXT:    retq
+entry:
+  %0 = load i128, i128* %b
+  %1 = add i128 %a, %0
+  store i128 %1, i128* %b
+  ret void
+}
+
 define i256 @add256(i256 %a, i256 %b) nounwind {
 ; CHECK-LABEL: add256:
 ; CHECK:       # %bb.0: # %entry