forked from OSchip/llvm-project
[SystemZ] Rename some Inst* instruction format classes
Now that we've added instruction format subclasses like InstRIb, it makes sense to rename the old InstRI to InstRIa. Similar for InstRX, InstRXY, InstRS, InstRSY, and InstSS. No functional change. llvm-svn: 286266
This commit is contained in:
Ulrich Weigand
parent
e833c6c61a
commit
37bd451a55
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@ -177,7 +177,7 @@ class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{7-0} = I1;
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}
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class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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@ -328,7 +328,7 @@ class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{7-0} = op{7-0};
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}
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class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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@ -483,7 +483,7 @@ class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{7-0} = op{7-0};
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}
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class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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@ -551,7 +551,7 @@ class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let HasIndex = 1;
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}
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class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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@ -585,7 +585,7 @@ class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let HasIndex = 1;
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}
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class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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@ -630,7 +630,7 @@ class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{15-0} = RI2;
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}
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class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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@ -708,7 +708,7 @@ class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Has20BitOffset = 1;
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}
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class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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@ -1165,7 +1165,7 @@ class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
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}
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class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstRI<0, outs, ins, asmstr, pattern> {
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: InstRIa<0, outs, ins, asmstr, pattern> {
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bits<32> enc;
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let Inst{31-24} = enc{31-24};
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@ -1181,7 +1181,7 @@ class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
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}
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class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstRIL<0, outs, ins, asmstr, pattern> {
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: InstRILa<0, outs, ins, asmstr, pattern> {
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bits<48> enc;
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string type;
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@ -1227,7 +1227,7 @@ class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
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}
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class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstRS<0, outs, ins, asmstr, pattern> {
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: InstRSa<0, outs, ins, asmstr, pattern> {
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bits<32> enc;
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let Inst{31-24} = enc{31-24};
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@ -1235,7 +1235,7 @@ class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
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// RSE is like RSY except with a 12 bit displacement (instead of 20).
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class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstRSY<6, outs, ins, asmstr, pattern> {
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: InstRSYa<6, outs, ins, asmstr, pattern> {
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bits <48> enc;
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let Inst{47-40} = enc{47-40};
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@ -1252,7 +1252,7 @@ class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
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}
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class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstRSY<0, outs, ins, asmstr, pattern> {
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: InstRSYa<0, outs, ins, asmstr, pattern> {
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bits<48> enc;
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let Inst{47-40} = enc{47-40};
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@ -1260,7 +1260,7 @@ class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
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}
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class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstRX<0, outs, ins, asmstr, pattern> {
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: InstRXa<0, outs, ins, asmstr, pattern> {
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bits<32> enc;
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let Inst{31-24} = enc{31-24};
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@ -1285,7 +1285,7 @@ class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
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}
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class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstRXY<0, outs, ins, asmstr, pattern> {
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: InstRXYa<0, outs, ins, asmstr, pattern> {
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bits<48> enc;
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let Inst{47-40} = enc{47-40};
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@ -1576,8 +1576,8 @@ class CallRR<string mnemonic, bits<8> opcode>
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mnemonic#"\t$R1, $R2", []>;
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class CallRX<string mnemonic, bits<8> opcode>
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: InstRX<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
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mnemonic#"\t$R1, $XBD2", []>;
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: InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
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mnemonic#"\t$R1, $XBD2", []>;
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class CondBranchRI<string mnemonic, bits<12> opcode,
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SDPatternOperator operator = null_frag>
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@ -1825,15 +1825,15 @@ class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
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class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
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AddressingMode mode = bdaddr12only>
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: InstRS<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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: InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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let mayLoad = 1;
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}
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class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
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AddressingMode mode = bdaddr20only>
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: InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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: InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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let mayLoad = 1;
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}
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@ -1869,9 +1869,9 @@ class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdxaddr12only>
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: InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(operator cls:$R1, mode:$XBD2)]> {
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: InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(operator cls:$R1, mode:$XBD2)]> {
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let OpKey = mnemonic ## cls;
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let OpType = "mem";
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let mayStore = 1;
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@ -1881,9 +1881,9 @@ class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdxaddr20only>
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: InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(operator cls:$R1, mode:$XBD2)]> {
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: InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(operator cls:$R1, mode:$XBD2)]> {
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let OpKey = mnemonic ## cls;
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let OpType = "mem";
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let mayStore = 1;
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@ -1924,15 +1924,15 @@ class StoreLengthVRSb<string mnemonic, bits<16> opcode,
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class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
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AddressingMode mode = bdaddr12only>
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: InstRS<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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: InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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let mayStore = 1;
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}
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class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
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AddressingMode mode = bdaddr20only>
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: InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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: InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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let mayStore = 1;
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}
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@ -2139,15 +2139,15 @@ multiclass CondUnaryRIEPair<string mnemonic, bits<16> opcode,
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class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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RegisterOperand cls, Immediate imm>
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: InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator imm:$I2))]>;
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: InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator imm:$I2))]>;
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class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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RegisterOperand cls, Immediate imm>
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: InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator imm:$I2))]>;
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: InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator imm:$I2))]>;
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class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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RegisterOperand cls>
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@ -2217,9 +2217,9 @@ multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
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class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdxaddr12only>
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: InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(set cls:$R1, (operator mode:$XBD2))]> {
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: InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(set cls:$R1, (operator mode:$XBD2))]> {
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let OpKey = mnemonic ## cls;
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let OpType = "mem";
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let mayLoad = 1;
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@ -2241,9 +2241,9 @@ class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdxaddr20only>
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: InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(set cls:$R1, (operator mode:$XBD2))]> {
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: InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(set cls:$R1, (operator mode:$XBD2))]> {
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let OpKey = mnemonic ## cls;
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let OpType = "mem";
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let mayLoad = 1;
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@ -2413,9 +2413,9 @@ multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
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class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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RegisterOperand cls, Immediate imm>
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: InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
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: InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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}
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@ -2440,18 +2440,18 @@ multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
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class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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RegisterOperand cls, Immediate imm>
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: InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
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: InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
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mnemonic#"\t$R1, $I2",
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[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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}
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class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls>
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: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
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mnemonic#"\t$R1, $BD2",
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[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
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: InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
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mnemonic#"\t$R1, $BD2",
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[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
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let R3 = 0;
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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@ -2459,9 +2459,9 @@ class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls>
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: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
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mnemonic#"\t$R1, $R3, $BD2",
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[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
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: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
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mnemonic#"\t$R1, $R3, $BD2",
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[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
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multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
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SDPatternOperator operator, RegisterOperand cls> {
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@ -2477,9 +2477,9 @@ multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
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class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
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AddressingMode mode = bdxaddr12only>
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: InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
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: InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
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let OpKey = mnemonic ## cls;
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let OpType = "mem";
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let Constraints = "$R1 = $R1src";
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@ -2506,9 +2506,9 @@ class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
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AddressingMode mode = bdxaddr20only>
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: InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
||||
mnemonic#"\t$R1, $XBD2",
|
||||
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
||||
: InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
||||
mnemonic#"\t$R1, $XBD2",
|
||||
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
||||
let OpKey = mnemonic ## cls;
|
||||
let OpType = "mem";
|
||||
let Constraints = "$R1 = $R1src";
|
||||
|
|
@ -2816,17 +2816,17 @@ class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|||
|
||||
class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
||||
RegisterOperand cls, Immediate imm>
|
||||
: InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
|
||||
mnemonic#"\t$R1, $I2",
|
||||
[(operator cls:$R1, imm:$I2)]> {
|
||||
: InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
|
||||
mnemonic#"\t$R1, $I2",
|
||||
[(operator cls:$R1, imm:$I2)]> {
|
||||
let isCompare = 1;
|
||||
}
|
||||
|
||||
class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
||||
RegisterOperand cls, Immediate imm>
|
||||
: InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
|
||||
mnemonic#"\t$R1, $I2",
|
||||
[(operator cls:$R1, imm:$I2)]> {
|
||||
: InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
|
||||
mnemonic#"\t$R1, $I2",
|
||||
[(operator cls:$R1, imm:$I2)]> {
|
||||
let isCompare = 1;
|
||||
}
|
||||
|
||||
|
|
@ -2846,9 +2846,9 @@ class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|||
class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
||||
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
||||
AddressingMode mode = bdxaddr12only>
|
||||
: InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
||||
mnemonic#"\t$R1, $XBD2",
|
||||
[(operator cls:$R1, (load mode:$XBD2))]> {
|
||||
: InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
||||
mnemonic#"\t$R1, $XBD2",
|
||||
[(operator cls:$R1, (load mode:$XBD2))]> {
|
||||
let OpKey = mnemonic ## cls;
|
||||
let OpType = "mem";
|
||||
let isCompare = 1;
|
||||
|
|
@ -2872,9 +2872,9 @@ class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|||
class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
||||
AddressingMode mode = bdxaddr20only>
|
||||
: InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
||||
mnemonic#"\t$R1, $XBD2",
|
||||
[(operator cls:$R1, (load mode:$XBD2))]> {
|
||||
: InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
||||
mnemonic#"\t$R1, $XBD2",
|
||||
[(operator cls:$R1, (load mode:$XBD2))]> {
|
||||
let OpKey = mnemonic ## cls;
|
||||
let OpType = "mem";
|
||||
let isCompare = 1;
|
||||
|
|
@ -3276,18 +3276,18 @@ multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
|
|||
|
||||
class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
RegisterOperand cls, AddressingMode mode = bdaddr20only>
|
||||
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
|
||||
mnemonic#"\t$R1, $R3, $BD2",
|
||||
[(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
|
||||
: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
|
||||
mnemonic#"\t$R1, $R3, $BD2",
|
||||
[(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
}
|
||||
|
||||
class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
||||
RegisterOperand cls, AddressingMode mode = bdaddr12only>
|
||||
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
||||
mnemonic#"\t$R1, $R3, $BD2",
|
||||
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
||||
: InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
||||
mnemonic#"\t$R1, $R3, $BD2",
|
||||
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
let mayLoad = 1;
|
||||
|
|
@ -3296,9 +3296,9 @@ class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|||
|
||||
class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
RegisterOperand cls, AddressingMode mode = bdaddr20only>
|
||||
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
||||
mnemonic#"\t$R1, $R3, $BD2",
|
||||
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
||||
: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
||||
mnemonic#"\t$R1, $R3, $BD2",
|
||||
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
let mayLoad = 1;
|
||||
|
|
@ -3550,9 +3550,9 @@ class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
|
|||
// another instruction to handle the excess.
|
||||
multiclass MemorySS<string mnemonic, bits<8> opcode,
|
||||
SDPatternOperator sequence, SDPatternOperator loop> {
|
||||
def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
|
||||
bdaddr12only:$BD2),
|
||||
mnemonic##"\t$BDL1, $BD2", []>;
|
||||
def "" : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
|
||||
bdaddr12only:$BD2),
|
||||
mnemonic##"\t$BDL1, $BD2", []>;
|
||||
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
|
||||
def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
|
||||
imm64:$length),
|
||||
|
|
|
|||
|
|
@ -650,22 +650,22 @@ def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>;
|
|||
let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1,
|
||||
DispKey = "la" in {
|
||||
let DispSize = "12" in
|
||||
def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
|
||||
"la\t$R1, $XBD2",
|
||||
[(set GR64:$R1, laaddr12pair:$XBD2)]>;
|
||||
def LA : InstRXa<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
|
||||
"la\t$R1, $XBD2",
|
||||
[(set GR64:$R1, laaddr12pair:$XBD2)]>;
|
||||
let DispSize = "20" in
|
||||
def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
|
||||
"lay\t$R1, $XBD2",
|
||||
[(set GR64:$R1, laaddr20pair:$XBD2)]>;
|
||||
def LAY : InstRXYa<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
|
||||
"lay\t$R1, $XBD2",
|
||||
[(set GR64:$R1, laaddr20pair:$XBD2)]>;
|
||||
}
|
||||
|
||||
// Load a PC-relative address. There's no version of this instruction
|
||||
// with a 16-bit offset, so there's no relaxation.
|
||||
let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
|
||||
isReMaterializable = 1 in {
|
||||
def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
|
||||
"larl\t$R1, $I2",
|
||||
[(set GR64:$R1, pcrel32:$I2)]>;
|
||||
def LARL : InstRILb<0xC00, (outs GR64:$R1), (ins pcrel32:$RI2),
|
||||
"larl\t$R1, $RI2",
|
||||
[(set GR64:$R1, pcrel32:$RI2)]>;
|
||||
}
|
||||
|
||||
// Load the Global Offset Table address. This will be lowered into a
|
||||
|
|
@ -1573,10 +1573,10 @@ let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
|
|||
[]>;
|
||||
|
||||
let hasSideEffects = 1 in {
|
||||
def EX : InstRX<0x44, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
|
||||
def EX : InstRXa<0x44, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
|
||||
"ex\t$R1, $XBD2", []>;
|
||||
def EXRL : InstRIL<0xC60, (outs), (ins GR64:$R1, pcrel32:$I2),
|
||||
"exrl\t$R1, $I2", []>;
|
||||
def EXRL : InstRILb<0xC60, (outs), (ins GR64:$R1, pcrel32:$RI2),
|
||||
"exrl\t$R1, $RI2", []>;
|
||||
}
|
||||
|
||||
let Defs = [CC] in {
|
||||
|
|
|
|||
Loading…
Reference in New Issue