forked from OSchip/llvm-project
Revert "[SelectionDAG] Extract [US]MULO expansion into TL method; NFC"
This reverts commit r353611. Triggers an assertion during the libcall expansion on ARM. llvm-svn: 353612
This commit is contained in:
Nikita Popov
parent
7de44ed945
commit
37bce93e36
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@ -3868,11 +3868,6 @@ public:
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/// integers as its arguments.
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SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
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/// Method for building the DAG expansion of ISD::[US]MULO, returning the two
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/// result values as a pair.
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std::pair<SDValue, SDValue> expandMULO(SDNode *Node,
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SelectionDAG &DAG) const;
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//===--------------------------------------------------------------------===//
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// Instruction Emitting Hooks
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//
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@ -136,6 +136,8 @@ private:
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bool &NeedInvert, const SDLoc &dl);
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SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
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SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
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unsigned NumOps, bool isSigned, const SDLoc &dl);
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std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
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SDNode *Node, bool isSigned);
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@ -2047,6 +2049,41 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
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return CallInfo.first;
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}
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/// Generate a libcall taking the given operands as arguments
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/// and returning a result of type RetVT.
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SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
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const SDValue *Ops, unsigned NumOps,
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bool isSigned, const SDLoc &dl) {
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TargetLowering::ArgListTy Args;
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Args.reserve(NumOps);
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TargetLowering::ArgListEntry Entry;
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for (unsigned i = 0; i != NumOps; ++i) {
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Entry.Node = Ops[i];
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Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
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Entry.IsSExt = isSigned;
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Entry.IsZExt = !isSigned;
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Args.push_back(Entry);
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}
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SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
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TLI.getPointerTy(DAG.getDataLayout()));
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Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
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TargetLowering::CallLoweringInfo CLI(DAG);
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CLI.setDebugLoc(dl)
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.setChain(DAG.getEntryNode())
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.setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
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std::move(Args))
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.setSExtResult(isSigned)
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.setZExtResult(!isSigned)
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.setIsPostTypeLegalization(true);
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std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
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return CallInfo.first;
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}
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// Expand a node into a call to a libcall. Similar to
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// ExpandLibCall except that the first operand is the in-chain.
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std::pair<SDValue, SDValue>
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@ -3321,9 +3358,110 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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}
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case ISD::UMULO:
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case ISD::SMULO: {
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auto Pair = TLI.expandMULO(Node, DAG);
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Results.push_back(Pair.first);
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Results.push_back(Pair.second);
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EVT VT = Node->getValueType(0);
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EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
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SDValue LHS = Node->getOperand(0);
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SDValue RHS = Node->getOperand(1);
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SDValue BottomHalf;
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SDValue TopHalf;
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static const unsigned Ops[2][3] =
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{ { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
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{ ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
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bool isSigned = Node->getOpcode() == ISD::SMULO;
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if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
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BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
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TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
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} else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
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BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
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RHS);
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TopHalf = BottomHalf.getValue(1);
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} else if (TLI.isTypeLegal(WideVT)) {
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LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
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RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
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Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
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BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
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DAG.getIntPtrConstant(0, dl));
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TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
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DAG.getIntPtrConstant(1, dl));
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} else {
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// We can fall back to a libcall with an illegal type for the MUL if we
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// have a libcall big enough.
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// Also, we can fall back to a division in some cases, but that's a big
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// performance hit in the general case.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (WideVT == MVT::i16)
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LC = RTLIB::MUL_I16;
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else if (WideVT == MVT::i32)
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LC = RTLIB::MUL_I32;
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else if (WideVT == MVT::i64)
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LC = RTLIB::MUL_I64;
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else if (WideVT == MVT::i128)
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LC = RTLIB::MUL_I128;
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
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SDValue HiLHS;
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SDValue HiRHS;
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if (isSigned) {
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// The high part is obtained by SRA'ing all but one of the bits of low
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// part.
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unsigned LoSize = VT.getSizeInBits();
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HiLHS =
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DAG.getNode(ISD::SRA, dl, VT, LHS,
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DAG.getConstant(LoSize - 1, dl,
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TLI.getPointerTy(DAG.getDataLayout())));
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HiRHS =
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DAG.getNode(ISD::SRA, dl, VT, RHS,
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DAG.getConstant(LoSize - 1, dl,
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TLI.getPointerTy(DAG.getDataLayout())));
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} else {
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HiLHS = DAG.getConstant(0, dl, VT);
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HiRHS = DAG.getConstant(0, dl, VT);
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}
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// Here we're passing the 2 arguments explicitly as 4 arguments that are
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// pre-lowered to the correct types. This all depends upon WideVT not
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// being a legal type for the architecture and thus has to be split to
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// two arguments.
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SDValue Ret;
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if(DAG.getDataLayout().isLittleEndian()) {
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// Halves of WideVT are packed into registers in different order
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// depending on platform endianness. This is usually handled by
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// the C calling convention, but we can't defer to it in
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// the legalizer.
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SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
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Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
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} else {
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SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
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Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
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}
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assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
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"Ret value is a collection of constituent nodes holding result.");
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BottomHalf = Ret.getOperand(0);
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TopHalf = Ret.getOperand(1);
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}
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if (isSigned) {
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Tmp1 = DAG.getConstant(
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VT.getSizeInBits() - 1, dl,
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TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
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Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
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TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
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ISD::SETNE);
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} else {
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TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
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DAG.getConstant(0, dl, VT), ISD::SETNE);
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}
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// Truncate the result if SetCC returns a larger type than needed.
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EVT RType = Node->getValueType(1);
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if (RType.getSizeInBits() < TopHalf.getValueSizeInBits())
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TopHalf = DAG.getNode(ISD::TRUNCATE, dl, RType, TopHalf);
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assert(RType.getSizeInBits() == TopHalf.getValueSizeInBits() &&
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"Unexpected result type for S/UMULO legalization");
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Results.push_back(BottomHalf);
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Results.push_back(TopHalf);
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break;
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}
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case ISD::BUILD_PAIR: {
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@ -5519,112 +5519,3 @@ TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo,
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DAG.getConstant(Scale, dl, ShiftTy));
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}
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std::pair<SDValue, SDValue> TargetLowering::expandMULO(
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SDNode *Node, SelectionDAG &DAG) const {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDLoc dl(Node);
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EVT VT = Node->getValueType(0);
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EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
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SDValue LHS = Node->getOperand(0);
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SDValue RHS = Node->getOperand(1);
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SDValue BottomHalf;
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SDValue TopHalf;
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static const unsigned Ops[2][3] =
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{ { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
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{ ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
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bool isSigned = Node->getOpcode() == ISD::SMULO;
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if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
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BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
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TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
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} else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
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BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
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RHS);
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TopHalf = BottomHalf.getValue(1);
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} else if (TLI.isTypeLegal(WideVT)) {
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LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
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RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
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SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
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BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Mul,
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DAG.getIntPtrConstant(0, dl));
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TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Mul,
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DAG.getIntPtrConstant(1, dl));
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} else {
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// We can fall back to a libcall with an illegal type for the MUL if we
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// have a libcall big enough.
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// Also, we can fall back to a division in some cases, but that's a big
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// performance hit in the general case.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (WideVT == MVT::i16)
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LC = RTLIB::MUL_I16;
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else if (WideVT == MVT::i32)
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LC = RTLIB::MUL_I32;
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else if (WideVT == MVT::i64)
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LC = RTLIB::MUL_I64;
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else if (WideVT == MVT::i128)
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LC = RTLIB::MUL_I128;
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
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SDValue HiLHS;
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SDValue HiRHS;
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if (isSigned) {
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// The high part is obtained by SRA'ing all but one of the bits of low
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// part.
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unsigned LoSize = VT.getSizeInBits();
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HiLHS =
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DAG.getNode(ISD::SRA, dl, VT, LHS,
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DAG.getConstant(LoSize - 1, dl,
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TLI.getPointerTy(DAG.getDataLayout())));
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HiRHS =
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DAG.getNode(ISD::SRA, dl, VT, RHS,
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DAG.getConstant(LoSize - 1, dl,
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TLI.getPointerTy(DAG.getDataLayout())));
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} else {
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HiLHS = DAG.getConstant(0, dl, VT);
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HiRHS = DAG.getConstant(0, dl, VT);
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}
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// Here we're passing the 2 arguments explicitly as 4 arguments that are
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// pre-lowered to the correct types. This all depends upon WideVT not
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// being a legal type for the architecture and thus has to be split to
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// two arguments.
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SDValue Ret;
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if(DAG.getDataLayout().isLittleEndian()) {
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// Halves of WideVT are packed into registers in different order
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// depending on platform endianness. This is usually handled by
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// the C calling convention, but we can't defer to it in
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// the legalizer.
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SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
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Ret = makeLibCall(DAG, LC, WideVT, Args, isSigned, dl).first;
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} else {
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SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
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Ret = makeLibCall(DAG, LC, WideVT, Args, isSigned, dl).first;
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}
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assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
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"Ret value is a collection of constituent nodes holding result.");
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BottomHalf = Ret.getOperand(0);
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TopHalf = Ret.getOperand(1);
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}
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EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
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if (isSigned) {
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SDValue ShiftAmt = DAG.getConstant(
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VT.getSizeInBits() - 1, dl,
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TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
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SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
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TopHalf = DAG.getSetCC(dl, SetCCVT, TopHalf, Sign, ISD::SETNE);
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} else {
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TopHalf = DAG.getSetCC(dl, SetCCVT, TopHalf,
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DAG.getConstant(0, dl, VT), ISD::SETNE);
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}
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// Truncate the result if SetCC returns a larger type than needed.
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EVT RType = Node->getValueType(1);
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if (RType.getSizeInBits() < TopHalf.getValueSizeInBits())
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TopHalf = DAG.getNode(ISD::TRUNCATE, dl, RType, TopHalf);
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assert(RType.getSizeInBits() == TopHalf.getValueSizeInBits() &&
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"Unexpected result type for S/UMULO legalization");
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return std::make_pair(BottomHalf, TopHalf);
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}
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