forked from OSchip/llvm-project
Use SDValue::getConstantOperandAPInt helper where possible. NFCI.
llvm-svn: 355267
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@ -3784,8 +3784,7 @@ bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
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return false;
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if (Op.getOpcode() == ISD::OR &&
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!MaskedValueIsZero(Op.getOperand(0),
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cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue()))
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!MaskedValueIsZero(Op.getOperand(0), Op.getConstantOperandAPInt(1)))
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return false;
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return true;
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@ -1712,7 +1712,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
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SDValue Sub = Op.getOperand(1);
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EVT SubVT = Sub.getValueType();
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unsigned NumSubElts = SubVT.getVectorNumElements();
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const APInt &Idx = cast<ConstantSDNode>(Op.getOperand(2))->getAPIntValue();
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const APInt &Idx = Op.getConstantOperandAPInt(2);
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if (Idx.ugt(NumElts - NumSubElts))
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break;
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unsigned SubIdx = Idx.getZExtValue();
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@ -2379,8 +2379,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
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N0.getOperand(0).getOpcode() == ISD::CTLZ &&
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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const APInt &ShAmt
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= cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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const APInt &ShAmt = N0.getConstantOperandAPInt(1);
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if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
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ShAmt == Log2_32(N0.getValueSizeInBits())) {
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if ((C1 == 0) == (Cond == ISD::SETEQ)) {
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@ -2531,8 +2530,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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// 8 bits, but have to be careful...
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if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
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origWidth = Lod->getMemoryVT().getSizeInBits();
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const APInt &Mask =
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cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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const APInt &Mask = N0.getConstantOperandAPInt(1);
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for (unsigned width = origWidth / 2; width>=8; width /= 2) {
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APInt newMask = APInt::getLowBitsSet(maskWidth, width);
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for (unsigned offset=0; offset<origWidth/width; offset++) {
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