From 378bb8014df60cce09f8807f726370dd01c8a544 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 16 Apr 2022 11:11:30 -0400 Subject: [PATCH] AMDGPU: Serialize a few more MachineFunctionInfo fields in MIR --- .../Target/AMDGPU/SIMachineFunctionInfo.cpp | 4 ++ .../lib/Target/AMDGPU/SIMachineFunctionInfo.h | 5 +++ .../AMDGPU/machine-function-info-after-pei.ll | 2 + .../AMDGPU/machine-function-info-no-ir.mir | 44 +++++++++++++++++++ .../MIR/AMDGPU/machine-function-info.ll | 8 ++++ 5 files changed, 63 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 1c6038f217f9..ef41ead17859 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -589,6 +589,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo( ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)), FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)), StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)), + BytesInStackArgArea(MFI.getBytesInStackArgArea()), + ReturnsVoid(MFI.returnsVoid()), ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) { for (Register Reg : MFI.WWMReservedRegs) WWMReservedRegs.push_back(regToString(Reg, TRI)); @@ -618,6 +620,8 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields( WaveLimiter = YamlMFI.WaveLimiter; HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs; HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs; + BytesInStackArgArea = YamlMFI.BytesInStackArgArea; + ReturnsVoid = YamlMFI.ReturnsVoid; if (YamlMFI.ScavengeFI) { auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo()); diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 0293880b31c3..252e334abe25 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -290,6 +290,9 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo { StringValue FrameOffsetReg = "$fp_reg"; StringValue StackPtrOffsetReg = "$sp_reg"; + unsigned BytesInStackArgArea = 0; + bool ReturnsVoid = true; + Optional ArgInfo; SIMode Mode; Optional ScavengeFI; @@ -323,6 +326,8 @@ template <> struct MappingTraits { StringValue("$fp_reg")); YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg, StringValue("$sp_reg")); + YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u); + YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true); YamlIO.mapOptional("argumentInfo", MFI.ArgInfo); YamlIO.mapOptional("mode", MFI.Mode, SIMode()); YamlIO.mapOptional("highBitsOf32BitAddress", diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll index 6873683ece6a..54b38a298184 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll @@ -18,6 +18,8 @@ ; AFTER-PEI-NEXT: scratchRSrcReg: '$sgpr68_sgpr69_sgpr70_sgpr71' ; AFTER-PEI-NEXT: frameOffsetReg: '$fp_reg' ; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32' +; AFTER-PEI-NEXT: bytesInStackArgArea: 0 +; AFTER-PEI-NEXT: returnsVoid: true ; AFTER-PEI-NEXT: argumentInfo: ; AFTER-PEI-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } ; AFTER-PEI-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir index c0a18bb76b80..995d908d0a2f 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -19,6 +19,8 @@ # FULL-NEXT: scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11' # FULL-NEXT: frameOffsetReg: '$sgpr12' # FULL-NEXT: stackPtrOffsetReg: '$sgpr13' +# FULL-NEXT: bytesInStackArgArea: 0 +# FULL-NEXT: returnsVoid: true # FULL-NEXT: argumentInfo: # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } # FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } @@ -114,6 +116,8 @@ body: | # FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' +# FULL-NEXT: bytesInStackArgArea: 0 +# FULL-NEXT: returnsVoid: true # FULL-NEXT: argumentInfo: # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } # FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } @@ -178,6 +182,8 @@ body: | # FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' +# FULL-NEXT: bytesInStackArgArea: 0 +# FULL-NEXT: returnsVoid: true # FULL-NEXT: argumentInfo: # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } # FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } @@ -243,6 +249,8 @@ body: | # FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' +# FULL-NEXT: bytesInStackArgArea: 0 +# FULL-NEXT: returnsVoid: true # FULL-NEXT: argumentInfo: # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } # FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } @@ -447,3 +455,39 @@ body: | S_ENDPGM 0 ... + +--- +# ALL-LABEL: name: bytes_in_stack_arg_area +# ALL: bytesInStackArgArea: 444 +name: bytes_in_stack_arg_area +machineFunctionInfo: + bytesInStackArgArea: 444 +body: | + bb.0: + SI_RETURN + +... + +--- +# ALL-LABEL: name: returns_void_true +# FULL: returnsVoid: true +# SIMPLE-NOT: returnsVoid +name: returns_void_true +machineFunctionInfo: + returnsVoid: true +body: | + bb.0: + SI_RETURN + +... +--- +# ALL-LABEL: name: returns_void_false +# ALL: returnsVoid: false +name: returns_void_false +machineFunctionInfo: + returnsVoid: false +body: | + bb.0: + SI_RETURN + +... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index da2836b42483..9b01a7967ae3 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -22,6 +22,8 @@ ; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' ; CHECK-NEXT: frameOffsetReg: '$fp_reg' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: bytesInStackArgArea: 0 +; CHECK-NEXT: returnsVoid: true ; CHECK-NEXT: argumentInfo: ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } ; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } @@ -62,6 +64,8 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { ; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' ; CHECK-NEXT: frameOffsetReg: '$fp_reg' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: bytesInStackArgArea: 0 +; CHECK-NEXT: returnsVoid: true ; CHECK-NEXT: argumentInfo: ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' } ; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } @@ -101,6 +105,8 @@ define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 { ; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' ; CHECK-NEXT: frameOffsetReg: '$sgpr33' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: bytesInStackArgArea: 0 +; CHECK-NEXT: returnsVoid: true ; CHECK-NEXT: argumentInfo: ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } ; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } @@ -143,6 +149,8 @@ define void @function() { ; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' ; CHECK-NEXT: frameOffsetReg: '$sgpr33' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: bytesInStackArgArea: 0 +; CHECK-NEXT: returnsVoid: true ; CHECK-NEXT: argumentInfo: ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } ; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }