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AMDGPU: Serialize a few more MachineFunctionInfo fields in MIR

This commit is contained in:
Matt Arsenault 2022-04-16 11:11:30 -04:00
parent f90f4884c8
commit 378bb8014d
5 changed files with 63 additions and 0 deletions
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4
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
View File

@ -589,6 +589,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
BytesInStackArgArea(MFI.getBytesInStackArgArea()),
ReturnsVoid(MFI.returnsVoid()),
ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
for (Register Reg : MFI.WWMReservedRegs)
WWMReservedRegs.push_back(regToString(Reg, TRI));
@ -618,6 +620,8 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields(
WaveLimiter = YamlMFI.WaveLimiter;
HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
BytesInStackArgArea = YamlMFI.BytesInStackArgArea;
ReturnsVoid = YamlMFI.ReturnsVoid;
if (YamlMFI.ScavengeFI) {
auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());

5
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
View File

@ -290,6 +290,9 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
StringValue FrameOffsetReg = "$fp_reg";
StringValue StackPtrOffsetReg = "$sp_reg";
unsigned BytesInStackArgArea = 0;
bool ReturnsVoid = true;
Optional<SIArgumentInfo> ArgInfo;
SIMode Mode;
Optional<FrameIndex> ScavengeFI;
@ -323,6 +326,8 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
StringValue("$fp_reg"));
YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
StringValue("$sp_reg"));
YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
YamlIO.mapOptional("mode", MFI.Mode, SIMode());
YamlIO.mapOptional("highBitsOf32BitAddress",

2
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
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@ -18,6 +18,8 @@
; AFTER-PEI-NEXT: scratchRSrcReg: '$sgpr68_sgpr69_sgpr70_sgpr71'
; AFTER-PEI-NEXT: frameOffsetReg: '$fp_reg'
; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32'
; AFTER-PEI-NEXT: bytesInStackArgArea: 0
; AFTER-PEI-NEXT: returnsVoid: true
; AFTER-PEI-NEXT: argumentInfo:
; AFTER-PEI-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
; AFTER-PEI-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }

44
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
View File

@ -19,6 +19,8 @@
# FULL-NEXT: scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11'
# FULL-NEXT: frameOffsetReg: '$sgpr12'
# FULL-NEXT: stackPtrOffsetReg: '$sgpr13'
# FULL-NEXT: bytesInStackArgArea: 0
# FULL-NEXT: returnsVoid: true
# FULL-NEXT: argumentInfo:
# FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
# FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }
@ -114,6 +116,8 @@ body: |
# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'
# FULL-NEXT: frameOffsetReg: '$fp_reg'
# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
# FULL-NEXT: bytesInStackArgArea: 0
# FULL-NEXT: returnsVoid: true
# FULL-NEXT: argumentInfo:
# FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
# FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }
@ -178,6 +182,8 @@ body: |
# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'
# FULL-NEXT: frameOffsetReg: '$fp_reg'
# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
# FULL-NEXT: bytesInStackArgArea: 0
# FULL-NEXT: returnsVoid: true
# FULL-NEXT: argumentInfo:
# FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
# FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }
@ -243,6 +249,8 @@ body: |
# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'
# FULL-NEXT: frameOffsetReg: '$fp_reg'
# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
# FULL-NEXT: bytesInStackArgArea: 0
# FULL-NEXT: returnsVoid: true
# FULL-NEXT: argumentInfo:
# FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
# FULL-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }
@ -447,3 +455,39 @@ body: |
S_ENDPGM 0
...
---
# ALL-LABEL: name: bytes_in_stack_arg_area
# ALL: bytesInStackArgArea: 444
name: bytes_in_stack_arg_area
machineFunctionInfo:
bytesInStackArgArea: 444
body: |
bb.0:
SI_RETURN
...
---
# ALL-LABEL: name: returns_void_true
# FULL: returnsVoid: true
# SIMPLE-NOT: returnsVoid
name: returns_void_true
machineFunctionInfo:
returnsVoid: true
body: |
bb.0:
SI_RETURN
...
---
# ALL-LABEL: name: returns_void_false
# ALL: returnsVoid: false
name: returns_void_false
machineFunctionInfo:
returnsVoid: false
body: |
bb.0:
SI_RETURN
...

8
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
View File

@ -22,6 +22,8 @@
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
; CHECK-NEXT: bytesInStackArgArea: 0
; CHECK-NEXT: returnsVoid: true
; CHECK-NEXT: argumentInfo:
; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
@ -62,6 +64,8 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
; CHECK-NEXT: bytesInStackArgArea: 0
; CHECK-NEXT: returnsVoid: true
; CHECK-NEXT: argumentInfo:
; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
@ -101,6 +105,8 @@ define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 {
; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
; CHECK-NEXT: frameOffsetReg: '$sgpr33'
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
; CHECK-NEXT: bytesInStackArgArea: 0
; CHECK-NEXT: returnsVoid: true
; CHECK-NEXT: argumentInfo:
; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }
@ -143,6 +149,8 @@ define void @function() {
; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
; CHECK-NEXT: frameOffsetReg: '$sgpr33'
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
; CHECK-NEXT: bytesInStackArgArea: 0
; CHECK-NEXT: returnsVoid: true
; CHECK-NEXT: argumentInfo:
; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }