From 377fc2aa3d477122e6fa943bd0a93c9f5b26e321 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Fri, 6 May 2016 21:10:43 +0000 Subject: [PATCH] [X86] Rename the X32_ADDR_ACCESS register class into LOW32_ADDR_ACCESS. This register class may be used by any ABIs that uses x86_64 ISA while using 32-bit addresses, not just in X32 cases. Make sure the name reflects that. llvm-svn: 268795 --- llvm/lib/Target/X86/X86RegisterInfo.cpp | 5 +++-- llvm/lib/Target/X86/X86RegisterInfo.td | 15 +++++++++------ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 5d2d072507b8..e32a5fdcdbaf 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -163,9 +163,10 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, if (Subtarget.isTarget64BitLP64()) return &X86::GR64RegClass; // If the target is 64bit but we have been told to use 32bit addresses, - // we can still use RIP-relative addresses. + // we can still use 64-bit register as long as we know the high bits + // are zeros. // Reflect that in the returned register class. - return Is64Bit ? &X86::X32_ADDR_ACCESSRegClass : &X86::GR32RegClass; + return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass; case 1: // Normal GPRs except the stack pointer (for encoding reasons). if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOSPRegClass; diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index 207182f0aaad..3c50ac7ce50a 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -415,14 +415,17 @@ def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, (and GR64_NOREX, GR64_NOSP)>; -// Register classes used for X32 address accesses. -// In X32 mode it is fine to use RIP as we are sure the 32 high bits -// are not set. -// We do not need variants for NOSP as RIP is not allowed there. +// Register classes used for ABIs that use 32-bit address accesses, +// while using the whole x84_64 ISA. + +// In such cases, it is fine to use RIP as we are sure the 32 high +// bits are not set. We do not need variants for NOSP as RIP is not +// allowed there. // Alignment is 64 because we have RIP. // FIXME: We could allow all 64bit registers, but we would need -// something to check that the 32 high bits are not set. -def X32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>; +// something to check that the 32 high bits are not set, +// which we do not have right now. +def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>; // A class to support the 'A' assembler constraint: EAX then EDX. def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;