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[RISCV] Use TargetConstant for CSR number for READ_CSR/WRITE_CSR. 

This is consistent with what we do for other operands that are required
to be constants.

I don't think this results in any real changes. The pattern match
code for isel treats ConstantSDNode and TargetConstantSDNode the same.
This commit is contained in:
Craig Topper 2021-11-08 15:05:27 -08:00
parent 28a06a1b87
commit 376233113e
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -5362,7 +5362,7 @@ SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op,
const MVT XLenVT = Subtarget.getXLenVT(); const MVT XLenVT = Subtarget.getXLenVT();
SDLoc DL(Op); SDLoc DL(Op);
SDValue Chain = Op->getOperand(0); SDValue Chain = Op->getOperand(0);
SDValue SysRegNo = DAG.getConstant( SDValue SysRegNo = DAG.getTargetConstant(
RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT); RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT);
SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other); SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other);
SDValue RM = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo); SDValue RM = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);
@ -5394,7 +5394,7 @@ SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
SDLoc DL(Op); SDLoc DL(Op);
SDValue Chain = Op->getOperand(0); SDValue Chain = Op->getOperand(0);
SDValue RMValue = Op->getOperand(1); SDValue RMValue = Op->getOperand(1);
SDValue SysRegNo = DAG.getConstant( SDValue SysRegNo = DAG.getTargetConstant(
RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT); RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT);
// Encoding used for rounding mode in RISCV differs from that used in // Encoding used for rounding mode in RISCV differs from that used in