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Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. 

llvm-svn: 138507
This commit is contained in:
Owen Anderson 2011-08-24 22:40:22 +00:00
parent 184bd1430b
commit 37612a3de3
2 changed files with 14 additions and 0 deletions
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1
llvm/lib/Target/ARM/ARMInstrThumb2.td
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@ -20,6 +20,7 @@ def it_pred : Operand<i32> {
// IT block condition mask
def it_mask : Operand<i32> {
let PrintMethod = "printThumbITMask";
let DecoderMethod = "DecodeITMask";
}
// Shifted operands. No register controlled shifts for Thumb2.

13
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -230,6 +230,8 @@ static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
@ -3304,3 +3306,14 @@ static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
return S;
}
static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
if (Mask == 0) {
Mask = 0x8;
CHECK(S, Unpredictable);
}
Inst.addOperand(MCOperand::CreateImm(Mask));
return S;
}