forked from OSchip/llvm-project
[X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr.
Summary: Due to missing parentheses. This is similar to https://reviews.llvm.org/D41983. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42062 llvm-svn: 322483
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@ -3595,8 +3595,7 @@ def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
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}
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let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
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hasSideEffects = 0, SchedRW = [WriteLoad] in {
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let Predicates = [HasAVX,NoVLX] in
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hasSideEffects = 0, SchedRW = [WriteLoad], Predicates = [HasAVX,NoVLX] in {
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def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"movdqa\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (alignedloadv2i64 addr:$src))],
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@ -3604,7 +3603,6 @@ def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
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"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
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VEX, VEX_L, VEX_WIG;
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let Predicates = [HasAVX,NoVLX] in
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def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (loadv2i64 addr:$src))],
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@ -3614,8 +3612,8 @@ def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
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XS, VEX, VEX_L, VEX_WIG;
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}
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let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
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let Predicates = [HasAVX,NoVLX] in
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let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore],
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Predicates = [HasAVX,NoVLX] in {
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def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
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(ins i128mem:$dst, VR128:$src),
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"movdqa\t{$src, $dst|$dst, $src}",
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@ -3625,7 +3623,6 @@ def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
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(ins i256mem:$dst, VR256:$src),
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"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
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VEX, VEX_L, VEX_WIG;
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let Predicates = [HasAVX,NoVLX] in
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def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",
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[(store (v2i64 VR128:$src), addr:$dst)], IIC_SSE_MOVU_P_MR>,
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