forked from OSchip/llvm-project
[CodeGen] Teach DAG combine to fold select_cc seteq X, 0, sizeof(X), ctlz_zero_undef(X) -> ctlz(X). InstCombine already does this for IR and X86 pattern matches this during isel.
A follow up commit will remove the X86 patterns to allow this to be tested. llvm-svn: 267325
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@ -14349,6 +14349,41 @@ SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
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}
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}
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// select_cc seteq X, 0, sizeof(X), ctlz(X) -> ctlz(X)
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// select_cc seteq X, 0, sizeof(X), ctlz_zero_undef(X) -> ctlz(X)
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// select_cc seteq X, 0, sizeof(X), cttz(X) -> cttz(X)
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// select_cc seteq X, 0, sizeof(X), cttz_zero_undef(X) -> cttz(X)
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// select_cc setne X, 0, ctlz(X), sizeof(X) -> ctlz(X)
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// select_cc setne X, 0, ctlz_zero_undef(X), sizeof(X) -> ctlz(X)
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// select_cc setne X, 0, cttz(X), sizeof(X) -> cttz(X)
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// select_cc setne X, 0, cttz_zero_undef(X), sizeof(X) -> cttz(X)
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if (N1C && N1C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
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SDValue ValueOnZero = N2;
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SDValue Count = N3;
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// If the condition is NE instead of E, swap the operands.
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if (CC == ISD::SETNE)
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std::swap(ValueOnZero, Count);
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// Check if the value on zero is a constant equal to the bits in the type.
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if (auto *ValueOnZeroC = dyn_cast<ConstantSDNode>(ValueOnZero)) {
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if (ValueOnZeroC->getAPIntValue() == VT.getSizeInBits()) {
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// If the other operand is cttz/cttz_zero_undef of N0, and cttz is
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// legal, combine to just cttz.
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if ((Count.getOpcode() == ISD::CTTZ ||
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Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
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N0 == Count.getOperand(0) &&
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(!LegalOperations || TLI.isOperationLegal(ISD::CTTZ, VT)))
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return DAG.getNode(ISD::CTTZ, DL, VT, N0);
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// If the other operand is ctlz/ctlz_zero_undef of N0, and ctlz is
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// legal, combine to just ctlz.
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if ((Count.getOpcode() == ISD::CTLZ ||
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Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) &&
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N0 == Count.getOperand(0) &&
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(!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT)))
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return DAG.getNode(ISD::CTLZ, DL, VT, N0);
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}
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}
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}
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return SDValue();
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}
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