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Fix a batch of x86 tests to be coalescer independent. 

Most of these tests require a single mov instruction that can come either before
or after a 2-addr instruction. -join-physregs changes the behavior, but the
results are equivalent.

llvm-svn: 130891
This commit is contained in:
Jakob Stoklund Olesen 2011-05-04 23:54:51 +00:00
parent d4a8cede47
commit 369bddf5ad
7 changed files with 38 additions and 29 deletions
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23
llvm/test/CodeGen/X86/sse3.ll
View File

@ -62,11 +62,10 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
ret <8 x i16> %tmp
; X64: t4:
; X64: pextrw $7, %xmm0, %eax
; X64: pshufhw $100, %xmm0, %xmm1
; X64: pinsrw $1, %eax, %xmm1
; X64: pextrw $1, %xmm0, %eax
; X64: movdqa %xmm1, %xmm0
; X64: pextrw $7, [[XMM0:%xmm[0-9]+]], %eax
; X64: pshufhw $100, [[XMM0]], [[XMM1:%xmm[0-9]+]]
; X64: pinsrw $1, %eax, [[XMM1]]
; X64: pextrw $1, [[XMM0]], %eax
; X64: pinsrw $4, %eax, %xmm0
; X64: ret
}
@ -251,13 +250,13 @@ entry:
%tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
ret <16 x i8> %tmp9
; X64: t16:
; X64: pinsrw $0, %eax, %xmm1
; X64: pextrw $8, %xmm0, %eax
; X64: pinsrw $1, %eax, %xmm1
; X64: pextrw $1, %xmm1, %ecx
; X64: movd %xmm1, %edx
; X64: pinsrw $0, %edx, %xmm1
; X64: pinsrw $1, %eax, %xmm0
; X64: pinsrw $0, %eax, [[X1:%xmm[0-9]+]]
; X64: pextrw $8, [[X0:%xmm[0-9]+]], %eax
; X64: pinsrw $1, %eax, [[X1]]
; X64: pextrw $1, [[X1]], %ecx
; X64: movd [[X1]], %edx
; X64: pinsrw $0, %edx, %xmm
; X64: pinsrw $1, %eax, %xmm
; X64: ret
}

6
llvm/test/CodeGen/X86/sse42.ll
View File

@ -12,7 +12,7 @@ define i32 @crc32_8(i32 %a, i8 %b) nounwind {
; X32: crc32b 8(%esp), %eax
; X64: _crc32_8:
; X64: crc32b %sil, %eax
; X64: crc32b %sil,
}
@ -23,7 +23,7 @@ define i32 @crc32_16(i32 %a, i16 %b) nounwind {
; X32: crc32w 8(%esp), %eax
; X64: _crc32_16:
; X64: crc32w %si, %eax
; X64: crc32w %si,
}
@ -34,5 +34,5 @@ define i32 @crc32_32(i32 %a, i32 %b) nounwind {
; X32: crc32l 8(%esp), %eax
; X64: _crc32_32:
; X64: crc32l %esi, %eax
; X64: crc32l %esi,
}

6
llvm/test/CodeGen/X86/tail-opts.ll
View File

@ -412,9 +412,9 @@ return:
; can fall-through into the ret and the other side has to branch anyway.
; CHECK: TESTE:
; CHECK: imulq
; CHECK-NEXT: LBB8_2:
; CHECK-NEXT: ret
; CHECK: ret
; CHECK-NOT: ret
; CHECK: size TESTE
define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone {
entry:

10
llvm/test/CodeGen/X86/use-add-flags.ll
View File

@ -7,10 +7,10 @@
; Use the flags on the add.
; CHECK: test1:
; CHECK: addl (%r[[A0:di|cx]]), {{%esi|%edx}}
; CHECK-NEXT: movl {{%edx|%r8d}}, %eax
; CHECK-NEXT: cmovnsl {{%ecx|%r9d}}, %eax
; CHECK-NEXT: ret
; CHECK: addl
; CHECK-NOT: test
; CHECK: cmovnsl
; CHECK: ret
define i32 @test1(i32* %x, i32 %y, i32 %a, i32 %b) nounwind {
%tmp2 = load i32* %x, align 4 ; <i32> [#uses=1]
@ -42,7 +42,7 @@ false:
; Do use the flags result of the and here, since the and has another use.
; CHECK: test3:
; CHECK: andl $16, %e[[A0]]
; CHECK: andl $16, %e
; CHECK-NEXT: jne
define void @test3(i32 %x) nounwind {

11
llvm/test/CodeGen/X86/vec_shuffle-16.ll
View File

@ -1,8 +1,9 @@
; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse
; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2
; sse: t1:
; sse2: t1:
define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind {
; sse: movaps
; sse: shufps
; sse2: pshufd
; sse2-NEXT: ret
@ -10,6 +11,8 @@ define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind {
ret <4 x float> %tmp1
}
; sse: t2:
; sse2: t2:
define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
; sse: shufps
; sse2: pshufd
@ -18,8 +21,9 @@ define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
ret <4 x float> %tmp
}
; sse: t3:
; sse2: t3:
define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
; sse: movaps
; sse: shufps
; sse2: pshufd
; sse2-NEXT: ret
@ -27,7 +31,10 @@ define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
ret <4 x float> %tmp
}
; sse: t4:
; sse2: t4:
define <4 x float> @t4(<4 x float> %A, <4 x float> %B) nounwind {
; sse: shufps
; sse2: pshufd
; sse2-NEXT: ret

9
llvm/test/CodeGen/X86/win64_alloca_dynalloca.ll
View File

@ -1,9 +1,12 @@
; RUN: llc < %s -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64
; RUN: llc < %s -mtriple=x86_64-win32-macho | FileCheck %s -check-prefix=EFI
; RUN: llc < %s -join-physregs -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64
; RUN: llc < %s -join-physregs -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64
; RUN: llc < %s -join-physregs -mtriple=x86_64-win32-macho | FileCheck %s -check-prefix=EFI
; PR8777
; PR8778
; Passing the same value in two registers creates a false interference that
; only -join-physregs resolves. It could also be handled by a parallel copy.
define i64 @foo(i64 %n, i64 %x) nounwind {
entry:

2
llvm/test/CodeGen/X86/x86-64-and-mask.ll
View File

@ -39,7 +39,7 @@ define void @ccc(i64 %x) nounwind {
; This requires a mov and a 64-bit and.
; CHECK: ddd:
; CHECK: movabsq $4294967296, %rax
; CHECK: movabsq $4294967296, %r
; CHECK: andq %rax, %rdi
define void @ddd(i64 %x) nounwind {