forked from OSchip/llvm-project
[PowerPC][NFC] Add test case in preparation for codegen change
This test case tests doubles inserted into vector ints, and help make apparent the optimizations a future patch will make.
This commit is contained in:
Albion Fung
parent
e4902480f1
commit
3678df5ae6
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@ -0,0 +1,305 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-LE-P9
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
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; xscvdpsxws and uxws is only available on Power7 and above
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; Codgen is different for LE Power7 and Power8
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define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
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; CHECK-LE-P7-LABEL: test:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI0_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI0_0@toc@l
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; CHECK-LE-P7-NEXT: lvx v3, 0, r4
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-LE-P7-NEXT: stw r3, -32(r1)
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; CHECK-LE-P7-NEXT: addi r3, r1, -32
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; CHECK-LE-P7-NEXT: lvx v4, 0, r3
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-LE-P8-NEXT: lvx v3, 0, r3
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; CHECK-LE-P8-NEXT: mffprwz r4, f0
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; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P9-NEXT: mffprwz r3, f0
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; CHECK-LE-P9-NEXT: mtfprwz f0, r3
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-BE-P7-NEXT: xxsldwi vs0, v2, v2, 3
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; CHECK-BE-P7-NEXT: stw r3, -32(r1)
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; CHECK-BE-P7-NEXT: addi r3, r1, -32
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; CHECK-BE-P7-NEXT: lxvw4x vs1, 0, r3
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; CHECK-BE-P7-NEXT: xxsldwi v2, vs0, vs1, 1
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P8-NEXT: mffprwz r3, f0
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; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
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; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
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; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
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; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P9-NEXT: mffprwz r3, f0
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; CHECK-BE-P9-NEXT: mtfprwz f0, r3
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
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; CHECK-BE-P9-NEXT: blr
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entry:
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%conv = fptosi double %b to i32
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%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
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ret <4 x i32> %vecins
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}
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define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
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; CHECK-LE-P7-LABEL: test2:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI1_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI1_0@toc@l
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; CHECK-LE-P7-NEXT: lvx v3, 0, r4
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-LE-P7-NEXT: stw r3, -32(r1)
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; CHECK-LE-P7-NEXT: addi r3, r1, -32
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; CHECK-LE-P7-NEXT: lvx v4, 0, r3
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test2:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-LE-P8-NEXT: lvx v3, 0, r3
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; CHECK-LE-P8-NEXT: mffprwz r4, f0
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; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test2:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P9-NEXT: mffprwz r3, f0
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; CHECK-LE-P9-NEXT: mtfprwz f0, r3
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test2:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-BE-P7-NEXT: xxsldwi vs0, v2, v2, 3
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; CHECK-BE-P7-NEXT: stw r3, -32(r1)
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; CHECK-BE-P7-NEXT: addi r3, r1, -32
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; CHECK-BE-P7-NEXT: lxvw4x vs1, 0, r3
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; CHECK-BE-P7-NEXT: xxsldwi v2, vs0, vs1, 1
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test2:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P8-NEXT: mffprwz r3, f0
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; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
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; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
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; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
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; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test2:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P9-NEXT: mffprwz r3, f0
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; CHECK-BE-P9-NEXT: mtfprwz f0, r3
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
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; CHECK-BE-P9-NEXT: blr
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entry:
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%conv = fptosi float %b to i32
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%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
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ret <4 x i32> %vecins
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}
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define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
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; CHECK-LE-P7-LABEL: test3:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI2_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI2_0@toc@l
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; CHECK-LE-P7-NEXT: lvx v3, 0, r4
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-LE-P7-NEXT: stw r3, -32(r1)
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; CHECK-LE-P7-NEXT: addi r3, r1, -32
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; CHECK-LE-P7-NEXT: lvx v4, 0, r3
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test3:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l
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; CHECK-LE-P8-NEXT: lvx v3, 0, r3
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; CHECK-LE-P8-NEXT: mffprwz r4, f0
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; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test3:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P9-NEXT: mffprwz r3, f0
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; CHECK-LE-P9-NEXT: mtfprwz f0, r3
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test3:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-BE-P7-NEXT: xxsldwi vs0, v2, v2, 3
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; CHECK-BE-P7-NEXT: stw r3, -32(r1)
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; CHECK-BE-P7-NEXT: addi r3, r1, -32
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; CHECK-BE-P7-NEXT: lxvw4x vs1, 0, r3
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; CHECK-BE-P7-NEXT: xxsldwi v2, vs0, vs1, 1
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test3:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P8-NEXT: mffprwz r3, f0
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; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
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; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
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; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
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; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test3:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P9-NEXT: mffprwz r3, f0
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; CHECK-BE-P9-NEXT: mtfprwz f0, r3
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
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; CHECK-BE-P9-NEXT: blr
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entry:
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%conv = fptoui double %b to i32
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%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
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ret <4 x i32> %vecins
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}
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define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
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; CHECK-LE-P7-LABEL: test4:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI3_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI3_0@toc@l
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; CHECK-LE-P7-NEXT: lvx v3, 0, r4
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-LE-P7-NEXT: stw r3, -32(r1)
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; CHECK-LE-P7-NEXT: addi r3, r1, -32
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; CHECK-LE-P7-NEXT: lvx v4, 0, r3
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test4:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
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; CHECK-LE-P8-NEXT: lvx v3, 0, r3
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; CHECK-LE-P8-NEXT: mffprwz r4, f0
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; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test4:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P9-NEXT: mffprwz r3, f0
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; CHECK-LE-P9-NEXT: mtfprwz f0, r3
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test4:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lwz r3, -4(r1)
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; CHECK-BE-P7-NEXT: xxsldwi vs0, v2, v2, 3
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; CHECK-BE-P7-NEXT: stw r3, -32(r1)
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; CHECK-BE-P7-NEXT: addi r3, r1, -32
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; CHECK-BE-P7-NEXT: lxvw4x vs1, 0, r3
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; CHECK-BE-P7-NEXT: xxsldwi v2, vs0, vs1, 1
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test4:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P8-NEXT: mffprwz r3, f0
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; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
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; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
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; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
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; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test4:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P9-NEXT: mffprwz r3, f0
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; CHECK-BE-P9-NEXT: mtfprwz f0, r3
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
|
||||
; CHECK-BE-P9-NEXT: blr
|
||||
entry:
|
||||
%conv = fptoui float %b to i32
|
||||
%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
|
||||
ret <4 x i32> %vecins
|
||||
}
|
||||
Loading…
Reference in New Issue